LE58QL02FJC Zarlink, LE58QL02FJC Datasheet - Page 31

• Manufacturer Part Number: LE58QL02FJC
• Description: SLIC 4-CH 3.3V 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE58QL02FJC

• Package: 44PLCC
• Number Of Channels Per Chip: 4
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

Notes:
*Transparent latch: Output follows input when EN is high; ouput holds last state when EN is low.
Debounce counter: Output is high after counting to programmed (DSH) number of 1 ms clocks; counter is reset for CD1 input changes at 125 µs
sample period. DSH0 - DSH3 programmed value is common for all four channels, but debounce counter is separate per channel.
Notes:
Programmed value of GK0 - GK3 determines clock rate (1 - 15 ms) of six-state counter.
If GK value = 0, the counter is bypassed and no buffering occurs.
Six-state up/down counter: Counts up when input is high; counts down when input is low.
Output goes and stays high when maximum count is reached; output goes and stays low when count is down to zero.
Real-Time Data Register Operation
To obtain time-critical data such as off/on-hook and ring trip information from the SLIC device with a minimum of processor time
and effort, the QLSLAC device contains an 8-bit Real Time Data register. This register contains CDA and CDB bits from all four
channels. The CDA bit for each channel is a debounced version of the CD1 input. The CDA bit is normally used for hook switch.
The CDB bit for each channel normally contains the debounced value of the CD2 input bit; however, if the E1 multiplex operation
is enabled, the CDB bit will contain the debounced value of the CD1B bit. CD1 and CD2 can be assigned to off-hook, ring trip,
ground key signals, or other signals. Frame sync is needed for the debounce and the ground key signals. If Frame sync is not
provided, the real-time register will not work. The register is read using MPI Command 4D/4Fh, and may be read at any time
regardless of the state of the Channel Enable Register. This allows off/on-hook, ring trip, or ground key information for all four
channels to be obtained from the QLSLAC device with one read operation versus one read per channel. If these data bits are not
used for supervision information, they can be accessed on an individual channel basis in the same way as C3–C5; however, CD1
and CD1B will not be debounced.
Interrupt
In addition to the Real Time Data register, an interrupt signal has been implemented in the QLSLAC device. The interrupt signal
is an active Low output signal which pulls Low whenever the unmasked CD bits change state (Low to High or High to Low); or
whenever the transmit PCM data changes on a channel in which the Arm Transmit Interrupt (ATI) bit is on. The interrupt control
is shown in
or open drain. When an interrupt is generated, all of the unmasked bits in the Real Time Data register latch and remain latched
until the interrupt is cleared. The interrupt is cleared by reading the register with Command 4Fh, by writing to the interrupt mask
register (Command 6Ch), or by a reset. If any of the inputs to the unmasked bits in the Real Time Data register are different from
Figure
FS (8 kHz)
21. The interrupt remains Low until the appropriate register is read. This output can be programmed as TTL
CD1
Sampling Interval
CD2 or CD1B
Ground-Key
D
GK0 – GK3
1 kHz
1 – 15 ms
Q
Clock Divider
(1 – 15 ms
clock output)
D
Figure 23. MPI Real-Time Data Register
RST
Q
a. Loop Detect Debounce Filter
Zarlink Semiconductor Inc.
b. Ground-Key Filter
D
Q
Six-State
Up/Down
Counter
UP/DN
31
Q
Debounce Period
8
DSH0 – DSH3
(0 – 15 ms)
MUX
Debounce Counter
GK = 0
GK = 0
CK
GK
RST
Q
CDB
D
EN/HOLD
*
Q
CDA