LE58QL02FJC Zarlink, LE58QL02FJC Datasheet - Page 40

• Manufacturer Part Number: LE58QL02FJC
• Description: SLIC 4-CH 3.3V 44-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of LE58QL02FJC

• Package: 44PLCC
• Number Of Channels Per Chip: 4
• Minimum Operating Supply Voltage: 3.135 V
• Typical Operating Supply Voltage: 3.3 V

QLSLAC devices and the individual CS lines will select the appropriate device to access. Between command sequences, DCLK
can stay in the High state indefinitely with no loss of internal control information regardless of any transitions on the CS lines.
Between bytes of a multibyte read or write command sequence, DCLK can also stay in the High state indefinitely. DCLK can stay
in the Low state indefinitely with no loss of internal control information, provided the CS lines remain at a High level.
If a low period of CS contains less than 8 positive DCLK transitions, it is ignored. If it contains 8 to 15 positive transitions, only
the last 8 transitions matter. If it contains 16 or more positive transitions, a hardware reset in the part occurs. If the chip is in the
middle of a read sequence when CS goes Low, data will be present at the DIO pin even if DCLK has no activity.
SUMMARY OF MPI COMMANDS
Note:
*All codes not listed are reserved by Legerity and should not be used.
MPI COMMAND STRUCTURE
This section details each MPI command. Each command is shown along with the format of any additional data bytes that follow.
For details of the filter coefficients of the form C
Unused bits are indicated by “RSVD”; 0’s should be written to them, but 0’s are not guaranteed when they are read.
*Default field values are marked by an asterisk. A hardware reset forces the default values.
6C/6Dh
C8/C9h
4A/4Bh
8A/8Bh
9A/9Bh
E8/E9h
40/41h
42/43h
44/45h
46/47h
50/51h
52/53h
54/55h
60/61h
70/71h
80/81h
82/83h
84/85h
86/87h
88/89h
96/97h
98/99h
Hex*
CDh
0Eh
4Dh
00h
02h
04h
06h
4Fh
73h
Deactivate (Standby state)
Software Reset
Hardware Reset
No Operation
Activate (Operational state)
Write/Read Transmit Time Slot and PCM Highway Selection
Write/Read Receive Time Slot and PCM Highway Selection
Write/Read REC & TX Clock Slot and TX Edge
Write/Read Configuration Register
Write/Read Channel Enable & Operating Mode Register
Read Real Time Data Register
Read Real Time Data Register and Clear Interrupt
Write/Read AISN and Analog Gains
Write/Read SLIC device Input/Output Register
Write/Read SLIC device Input/Output Direction and Status Bits
Write/Read Operating Functions
Write/Read Interrupt Mask Register
Write/Read Operating Conditions
Read Revision Code Number (RCN)
Write/Read GX Filter Coefficients
Write/Read GR Filter Coefficients
Write/Read Z Filter Coefficients (FIR and IIR)
Write/Read B1 Filter Coefficients (FIR)
Write/Read X Filter Coefficients
Write/Read R Filter Coefficients
Write/Read B2 Filter Coefficients (IIR)
Write/Read Z Filter Coefficients (FIR only)
Write/Read Z Filter Coefficients (IIR only)
Write/Read Debounce Time Register
Read Transmit PCM Data
Write/Read Ground Key Filter Sampling Interval
xy
m
xy
Zarlink Semiconductor Inc.
, refer to the General Description of CSD Coefficients section
40
Description
page
56.