SI5366-C-GQR Silicon Laboratories Inc, SI5366-C-GQR Datasheet - Page 10

• Manufacturer Part Number: SI5366-C-GQR
• Description: IC CLOCK MULTIPLIER PREC 100TQFP
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5366-C-GQR

• Input: *
• Output: *
• Frequency - Max: *
• Voltage - Supply: *
• Operating Temperature: *
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Si5366
10
Pin #
22
29
30
32
42
34
35
37
39
40
44
45
49
AUTOSEL
Pin Name
DBL2_BY
CKIN4+
CKIN2+
CKIN3+
CKIN1+
CKIN4–
CKIN2–
CKIN3–
CKIN1–
RATE0
RATE1
LOL
Table 3. Si5366 Pin Descriptions (Continued)
I/O
O
I
I
I
I
I
I
I
Signal Level
LVCMOS
3-Level
3-Level
3-Level
MULTI
MULTI
MULTI
MULTI
Preliminary Rev. 0.3
Manual/Automatic Clock Selection.
Three level input that selects the method of input clock selec-
tion to be used.
L = Manual.
M = Automatic non-revertive.
H = Automatic revertive.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tri-
state.
Clock Input 4.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN4 serves as the frame sync input asso-
ciated with the CKIN2 clock when CK_CONF = 1.
External Crystal or Reference Clock Rate.
Three-level inputs that select the type and rate of external crys-
tal or reference clock to be applied to the XA/XB port. Refer to
the Family Reference Manual for settings. These pins have
both a weak pull-up and a weak pull-down and default to M.
Some designs may require an external resistor voltage divider
when driven by an active device.
Clock Input 2.
Differential input clock. This input can also be driven with a sin-
gle-ended signal.
CKOUT2 Disable/PLL Bypass Mode Control.
Controls enable of CKOUT2 divider/output buffer path and PLL
bypass mode.
L = CKOUT2 Enabled.
M = CKOUT2 Disabled.
H = BYPASS Mode with CKOUT2 enabled.
This pin has both weak pull-ups and weak pull-downs and
defaults to M. Some designs may require an external resistor
voltage divider when driven by an active device that will tri-
state.
Clock Input 3.
Differential clock input. This input can also be driven with a sin-
gle-ended signal. CKIN3 serves as the frame sync input asso-
ciated with the CKIN1 clock when CK_CONF = 1.
Clock Input 1.
Differential clock input. This input can also be driven with a sin-
gle-ended signal.
PLL Loss of Lock Indicator.
This pin functions as the active high PLL loss of lock indicator.
0 = PLL locked.
1 = PLL unlocked.
Description