HI7188IN Intersil, HI7188IN Datasheet - Page 12

• Manufacturer Part Number: HI7188IN
• Description: CONV A/D 16BIT 8:1 MUX 44-MQFP
• Manufacturer: Intersil

Specifications of HI7188IN

• Number Of Bits: 16
• Sampling Rate (per Second): 240
• Data Interface: QSPI™, Serial, SPI™
• Number Of Converters: 1
• Power Dissipation (max): 50mW
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Where C
modulator sampling rate set by the master clock divided by
six (F
Bipolar/Unipolar Input Ranges
The inputs can accept either unipolar or bipolar input
voltages with each physical channel’s mode being
independent of other physical channels. Bipolar or unipolar
options are chosen by programming the bipolar/unipolar
(B/U) bits of the Channel Configuration Registers (CCR).
Programming the logical channels for either unipolar or
bipolar operation does not change any of the input signal
conditioning. The inputs are differential, and as a result are
referenced to the voltage on the V
V
unipolar operation with a gain of 1 and a V
input voltage range on the V
V
bipolar mode with gain of 1 and a V
input range on the V
Multiplexer
The input multiplexer is a fully differential 8 channel device
controlled by the internal microsequencer. Any number of
inputs, up to 8, can be scanned and both the number of
physical channels scanned and the scanning order are
controlled by the users programming of the Channel
Configuration Register (CCR). The output of the multiplexer
feeds the input to the Programmable Gain Instrumentation
Amplifier (PGIA).
External Multiplexers
For interfacing the HI7188 to external multiplexers several
output pins are available. These pins include MXC, A
and A
during the modulator and integrating filter reset pulse. The
pulse width is typically 14.6 s with LNR disabled and 54.6 s
with LNR enabled. This signal can be used to “break before
make” an external multiplexer. Referring to Figure 9, the data
conversion time involves the actual input channel A/D
conversion while the calibration time involves data
calibration and coding of the conversion results. The address
pins A
currently being converted. The user can utilize these output
pins to drive external multiplexer address pins.
INHX
INLX
GAIN
S
0
TABLE 2. EFFECTIVE INPUT IMPEDANCE vs GAIN
2,
is +1.25V and logical channel X is configured for
1
2
4
8
is +3.75V and logical channel X is configured for
. Refer to Figure 9. The MXC pulse is active high
= 3.6864MHz/6 = 614.4kHz).
A
S
1
is the internal sampling capacitance and F
and A
SAMPLING
0
describe the logical address which is
RATE
614.4
614.4
614.4
614.4
(kHz)
INHX
input is -1.25V to +3.75V.
INLX
12
CAPACITOR
SAMPLING
input is +1.25V to +3.75V. If
INL
REF
(pF)
16
32
4
8
input. For example, if
of +2.5V, the analog
REF
IMPEDANCE
of +2.5V, the
INPUT
(k )
407
203
102
51
S
2,
is the
A
1
HI7188
The main critical issue is the external multiplexer output
must switch and settle to 0.00153% (16 bits) of the final
value during the MXC reset pulse and prior to Data
Integration or data errors will occur. The input must be stable
only during the data integration period but can be changed
during the calibration period.
Programmable Gain Instrumentation Amplifier
The Programmable Gain Instrumentation Amplifier (PGIA)
allows the user to interface low level sensors and bridges
directly to the HI7188. The PGIA has 4 selectable gain
options of 1, 2, 4, and 8. The gain of each physical channel
is independent of other physical channels and is
programmable by writing the G1 and G0 bits in the Channel
Configuration Registers (CCR).
Differential Reference Input
The reference inputs, V
reference input capability. V
V
range for these differential inputs is from AV
the nominal differential voltage (V
+2.5V. Larger values of V
degradation in performance. Smaller values of V
also be used but performance will be degraded since the
system noise is larger relative to the LSB size. The full scale
range of the HI7188 is defined as:
FSR
FSR
The reference inputs provide a high impedance dynamic
load similar to the analog inputs. For proper circuit operation
these pins must be driven by low impedance circuitry.
Reference noise outside of the band of interest will be
removed by the digital filter but excessive reference noise
inside the band of interest will degrade performance.
V
The V
HI7188 analog circuitry and should always be tied to the
midpoint of the AV
provides a common mode input voltage for the internal
operational amplifiers and must be driven from a low noise,
low impedance source if it is not tied to analog ground.
Failure to do so will result in degraded HI7188 performance.
C
A
RLO
ADDR
CM
2, 1, 0
MXC
UNIPOLAR
BIPOLAR
Input
CM
for proper operation of the device. The common mode
VALID LOGICAL ADDRESS
CONVERSION CALIBRATION
input is the internal reference voltage for the
FIGURE 9. CHANNEL SWITCHING TIMING
DATA
= 2 x V
= V
DD
REF
REF
and AV
/GAIN
RHI
REF
/GAIN
and V
RHI
SS
can be used with minor
must always be greater than
supplies. This point
RLO
REF
SWITCH
CHAN
VALID LOGICAL ADDRESS
t
MXC
, provide a differential
= V
RHI
CONVERSION
SS
DATA
- V
to AV
REF
RLO
DD
) is
can
and