AD5627BRMZ Analog Devices Inc, AD5627BRMZ Datasheet - Page 9

• Manufacturer Part Number: AD5627BRMZ
• Description: IC DAC NANO 12BIT DUAL 10-MSOP
• Manufacturer: Analog Devices Inc
• Series: nanoDAC™r

Specifications of AD5627BRMZ

• Data Interface: Serial
• Settling Time: 3µs
• Number Of Bits: 12
• Number Of Converters: 2
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 5.75mW
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Resolution (bits): 12bit
• Sampling Rate: 333kSPS
• Input Channel Type: Serial
• Supply Voltage Range - Analog: 2.7V To 5.5V
• Supply Current: 950µA
• Digital Ic Case Style: SOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions
Pin
No.
1
2
3
4
5
6
7
8
9
10
V
V
GND
LDAC
CLR
ADDR
SCL
SDA
V
V
Mnemonic
OUT
OUT
DD
REFIN
A
B
/V
Figure 4. AD5627/AD5667 Pin Configuration
REFOUT
V
V
LDAC
OUT
OUT
GND
CLR
EXPOSED PAD TIED TO GND
A
B
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the part.
Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows
simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.
Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored.
When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The part exits
clear code mode on the falling edge of the 9
write sequence, the write is aborted. If CLR is activated during high speed mode the part will exit high speed mode.
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
The AD56x7R have a common pin for reference input and reference output. When using the internal reference, this is
the reference output pin. When using an external reference, this is the reference input pin. The default for this pin is
as a reference input. (The internal reference and reference output are only available on R suffix versions.) The AD56x7
has a reference input pin only.
ON LFCSP PACKAGE.
1
2
3
4
5
(Not to Scale)
AD5627/
AD5667
TOP VIEW
10
9
8
7
6
V
V
SDA
SCL
ADDR
REFIN
DD
Rev. 0 | Page 9 of 32
AD5627R/AD5647R/AD5667R, AD5627/AD5667
th
clock pulse of the last byte of valid write. If CLR is activated during a
Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration
V
V
LDAC
OUT
OUT
GND
CLR
EXPOSED PAD TIED TO GND
A
B
ON LFCSP PACKAGE.
1
2
3
4
5
(Not to Scale)
AD5627R/
AD5647R/
AD5667R
TOP VIEW
10
9
8
7
6
V
V
SDA
SCL
ADDR
REFIN
DD
/V
REFOUT