PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 12

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

List of Figures
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Data Sheet
Block Diagram of the DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block Diagram of the DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
DELIC-LC in S/T and UPN Line Cards (up to 8 S/T and 16 UPN). . . . . 7
DELIC-LC/PB in Uk0 Line Card for 16 Subscribers. . . . . . . . . . . . . . . . 8
DELIC-PB in Analog Line Card for 16 Subscribers . . . . . . . . . . . . . . . . 8
DELIC-PB in Small PBX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
DELIC-PB in 4 Port SDSL Line Card . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration DELIC-LC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Pin Configuration DELIC-PB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Overview of IOM-2000 Interface Structure (Example with One VIP) . . 41
IOM-2000 Data Sequence (1 VIP with 8 Channels) . . . . . . . . . . . . . . 43
IOM-2000 Data Order (3 VIPs with 24 Channels) . . . . . . . . . . . . . . . . 44
IOM-2000 CMD/STAT Handling (1 VIP with 8 Channels) . . . . . . . . . . 45
IOM-2000 Command/Status Sequence (3 VIPs with 24 Channels) . . 45
UPN State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
State Diagram of LT-S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
LT-T Mode State Diagram (Conditional and Unconditional States) . . . 60
IOM®-2 Interface in Digital Line Card Mode . . . . . . . . . . . . . . . . . . . . 63
DELIC in Multiplexed and in De-Multiplexed Bus Mode . . . . . . . . . . . 65
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
U
AMI Coding on the Up Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Handling of UPN Frame (one Channel) . . . . . . . . . . . . . . . . . . . . . . . . 79
S/T Interface Line Code (without code violation) . . . . . . . . . . . . . . . . . 83
Frame Structure at Reference Points S and T (ITU I.430). . . . . . . . . . 84
Reference Clock Selection for Cascaded VIPs on IOM-2000 . . . . . . . 85
Handling of So Frame in LT-S Mode (One Channel) . . . . . . . . . . . . . . 86
D-Echo Bit Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Handling of So Frame in LT-T Mode (One Channel) . . . . . . . . . . . . . . 88
Collision Detection in the LT-T Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 90
S/Q Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
IOMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
IOMU Frame-Wise Circular-Buffer Architecture. . . . . . . . . . . . . . . . . . 98
The Circular-Buffer During two Consecutive Frames. . . . . . . . . . . . . . 99
IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 101
IOM-2 Interface Open-Drain Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 102
IOM-2 Interface Push-Pull Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
DRDY Signal Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
DRDY Sampling Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
PCMU Integration in DELIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
IOM-2 Interface Timing in Single/Double Clock Mode . . . . . . . . . . . . 108
PN
Interface Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PEB 20570
PEB 20571
2003-07-31
Page