PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 155

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

• A 4-bit Interrupt status register (DINSTA), which actually belongs to both directions -
The DELIC initiates all transfers, i.e. each transmit is initiated by the OAK. But the
transfers are carried out by the DMA controller.
If the DELIC transmits data e.g. to the GHDLC unit, the OAK writes the requested
number of bytes (minus 1) into the DTXCNT register which causes the assertion of
DREQT (“DMA Request for Transmit direction”) pin.
The DMA controller grants the bus to the DELIC, it drives DACK low and begins toggling
the control lines.
In Intel / Infineon (Memory-to-Memory) mode it drives WR line low when writing a byte
to the mailbox. RD line stays high during all the “Write” transfer. DACK functions as a CS
and is driven low during each “Write” access. Refer to AC specification, in
Figure 55
In Motorola (Memory-to-Memory) mode the DMA controller drives R/W line low during
‘Write’ operations when DACK is low and DS is used for access timing. In Fly-by mode
the meaning of ‘Read’ and ‘Write’ commands is opposite for the mailbox
Chapter
by one. DMA-operation is finished with the count down from ´0
The DMA controller can stop the transaction (before frame end) driving DACK high. The
DELIC continues keeps DREQT active, stops decrementing DTXCNT and waits until
DACK becomes low again.
Data Sheet
DREQT
DSP-tasks
DACK
WR
Transmit and Receive.
4.10.1.2). After every ‘Write’ operation the counter (DTXCNT) is decremented
Timing in two-cycle DMA Mode for Transmit Direction and Infineon/
Intel Bus Type
WR
DTXCNT
1
2
138
16
OAK -
INT0
ISR:
WR DTXCNT
H
Functional Description
´ to the value ’F
PEB 20570
PEB 20571
Chapter
2003-07-31
H
’.
(see
8.