PEB20570FV3.1T Infineon Technologies, PEB20570FV3.1T Datasheet - Page 96

• Manufacturer Part Number: PEB20570FV3.1T
• Manufacturer: Infineon Technologies

Specifications of PEB20570FV3.1T

• Lead Free Status / Rohs Status: Not Compliant

4.2.6
The data is received and transmitted at a nominal bit rate of 384 kbit/s. In the first half of
the 4 KHz frame data is transmitted and ‘zeros’ are received, in the second half of the
frame ‘zeros’ are transmitted and data is received (Ping-pong interface).
Figure 24
Transmit Direction
• Since the DELIC is always master on the Up-interface, all transmitted Up frames
• The LF-bit is generated and inserted at the beginning of the frame.
• B-channel data prepared by the DSP is scrambled and inserted into the U-frame.
• D- channel data and M-bit, prepared by the DSP, are inserted into the transmitted Up
Receive Direction
• The received frame start is recognized by the LF-bit, which is always logical ‘1’ (this is
• The B-channel data is descrambled
• The B- and D-channel data and M-bit are stored in the Data RAM
Data Sheet
always start with the FSC-2000 (the transmission starts from ch-0.bit-0 which is
followed by ch_1.bit_0, ch_2.bit_0,... ch_7.bit_0, ch_1.bit_1, etc.; see also
frame by the TRANSIU.
the first ‘1’ received after the FSC_2000). Since the received frames start at different
points of time (due to the different line delays) the frame start recognition is performed
for each channel separately
Rx
Tx
Rx:
VIP hardware:
FIFOs:
- for jitter compensation
DC-bit generation
Tx:
VIP hardware:
VIP
DC
Rx FIFO
U
PN
Handling of U
Interface
PN
TRANSIU
TRANSIU hardware:
LF-bit recognition
DC-bit discard
B-channel descrambling
B-channel scrambling
LF-bit generation
IOM-2000 hardware:
Machine SYNC
Frame (one Channel)
State
Tx buffer
Rx buffer
79
250 µs
F
CV
DSP software:
Generation of complete Up frame
M-bit handling
Functional Description
DSP software:
M-bit handling
DSP
PEB 20570
PEB 20571
Figure
2003-07-31
DELIC
12)