KU82596DX25 S Z714 Intel, KU82596DX25 S Z714 Datasheet - Page 47

• Manufacturer Part Number: KU82596DX25 S Z714
• Manufacturer: Intel

Specifications of KU82596DX25 S Z714

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

where
EOF
SIZE (ACT COUNT)
NEXT TBD ADDRESS
BUFFER ADDRESS
TDR
This operation activates Time Domain Reflectometry which is a mechanism to detect open or short circuits on
the link and their distance from the diagnosing station The TDR command has no parameters The TDR
transmit sequence was changed compared to the 82586 to form a regular transmission The TDR command
is designed to be used statically Make sure that both the CU and RU are idle before attempting a TDR
command The TDR bit stream is as follows
Maximum length of the TDR frame is 2048 bits If the 82596 senses collision while transmitting the TDR frame
it transmits the jam pattern and stops the transmission The 82596 then triggers an internal timer (STC) the
timer is reset at the beginning of transmission and reset if CRS is returned The timer measures the time
elapsed from the start of transmission until an echo is returned The echo is indicated by Collision Detect going
active or a drop in the Carrier Sense signal The following table lists the possible cases that the 82596 is able
to analyze
An Ethernet transceiver is defined as one that returns transmitted data on the receive pair and activates the
Carrier Sense Signal while transmitting A Non-Ethernet Transceiver is defined as one that does not do so
Condition
Carrier Sense was inactive for 2048-bit-time
periods
Carrier Sense signal dropped
Collision Detect went active
The Carrier Sense Signal did not drop or the
Collision Detect did not go active within
2048-bit time period
Preamble
Source address
Another Source address (the TDR frame is transmitted back to the sending station
so DEST ADR
Data field containing 7Eh patterns
Jam Pattern which is the inverse CRC of the transmitted frame
e
SRC ADR)
This bit indicates that this TBD is the last one associated with the frame being
transmitted It is set by the CPU before transmit
This 14-bit quantity specifies the number of bytes that hold information for the
current buffer It is set by the CPU before transmission
In the 82586 and 32-bit Segmented modes it is the offset of the next TBD on the
list In the Linear mode this is the 32-bit address of the next TBD on the list It is
meaningless if EOF
The starting address of the memory area that contains the data to be sent In the
82586 mode this is a 24-bit address (A31 – A24 are considered to be zero) In the
32-bit Segmented and Linear modes this is a 32-bit address This buffer can be
byte aligned for the 82596 B-step
Conditions of TDR as Interpreted by the 82596
Transceiver Type
e
1
Short or Open on the
Transceiver Cable
Short on the Ethernet cable
Open on the Ethernet cable
No Problem
Ethernet
NA
NA
Open on the Serial Link
No Problem
Non Ethernet
82596DX SX
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