AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 10

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
SYNCHRONOUS READ/WRITE—BUS MASTER
Use these specifications for interfacing to external memory systems that require CLKIN—relative timing or for accessing a slave
ADSP 2106x in multiprocessor memory space. These synchronous switching characteristics are also valid during asynchronous memory
reads and writes (see the Memory Read—Bus Master and Memory Write—Bus Master sections).
When accessing a slave ADSP-2106x, these switching characteristics must meet the slave’s timing requirements for synchronous
read/writes (see the Synchronous Read/Write—Bus Slave section). The slave ADSP-2106x must also meet these bus master timing
requirements for data and acknowledge setup and hold times.
Table 10. Specifications
Parameter
Timing Requirements:
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
t
t
t
t
t
t
t
W = number of wait states specified in WAIT register × t
1
2
3
SSDATI
HSDATI
DAAK
SACKC
HACKC
DADRO
HADRO
DPGC
DRDO
DWRO
DRWL
SDDATO
DATTR
DADCCK
ADRCK
ADRCKH
ADRCKL
For MS x, SW , BMS , the falling edge is referenced.
ACK delay/setup: User must meet t
See the
System Hold Time Calculation Example
Data Setup before CLKIN
Data Hold after CLKIN
ACK Delay after Address, MSx, SW, BMS
ACK Setup before CLKIN
ACK Hold after CLKIN
Address, MSx, BMS, SW, Delay after CLKIN
Address, MSx, BMS, SW, Hold after CLKIN
PAGE Delay after CLKIN
RD High Delay after CLKIN
WR High Delay after CLKIN
RD/WR Low Delay after CLKIN
Data Delay after CLKIN
Data Disable after CLKIN
ADRCLK Delay after CLKIN
ADRCLK Period
ADRCLK Width High
ADRCLK Width Low
DAAK
, t
DSAK
2
3
, or synchronous specification, t
section for the calculation of hold times given capacitive and dc loads.
CK
.
1, 2
1
Min
3 + DT/8
4 − DT/8
6.5 + DT/4
−0.5 − DT/4
−1 − DT/8
9 + DT/8
−2 − DT/8
−3 − 3 DT/16
8 + DT/4
0 − DT/8
4 + DT/8
t
(t
(t
CK
CK
CK
/2 − 2)
/2 − 2)
Rev. B | Page 10 of 48
SACKC
.
5 V
Max
13.5 + 7 DT/8 + W
8 − DT/8
17 + DT/8
+5 − DT/8
+5 − 3 DT/16
13.5 + DT/4
20 + 5 DT/16
8 − DT/8
11 + DT/8
Min
3 + DT/8
4 − DT/8
6.5 + DT/4
−0.5 − DT/4
−1 − DT/8
9 + DT/8
−2 − DT/8
−3 − 3 DT/16
8 + DT/4
0 − DT/8
4 + DT/8
t
(t
(t
CK
CK
CK
/2 − 2)
/2 − 2)
3.3 V
17 + DT/8
13.5 + DT/4
11 + DT/8
Max
13.5 + 7 DT/8 + W
8 − DT/8
+5 − DT/8
+5 − 3 DT/16
20.25 + 5 DT/16
8 – DT/8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns