AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 23

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

Table 18. Serial Ports
Parameter
External Clock
Timing Requirements:
t
t
t
t
t
t
Internal Clock
Timing Requirements:
t
t
t
t
External or Internal Clock
Switching Characteristics:
t
t
External Clock
Switching Characteristics:
t
t
t
t
Internal Clock
Switching Characteristics:
t
t
t
t
t
Enable and Three-State
Switching Characteristics:
t
t
t
t
t
t
Gated SCLK with External TFS (Mesh Multiprocessing)
Timing Requirements:
t
t
SFSE
HFSE
SDRE
HDRE
SCLKW
SCLK
SFSI
HFSI
SDRI
HDRI
DFSE
HFSE
DFSE
HFSE
DDTE
HDTE
DFSI
HFSI
DDTI
HDTI
SCLKIW
DDTEN
DDTTE
DDTIN
DDTTI
DCLK
DPTR
STFSCK
HTFSCK
TFS/RFS Setup before TCLK/RCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
TCLK/RCLK Width
TCLK/RCLK Period
TFS Setup before TCLK
TFS/RFS Hold after TCLK/RCLK
Receive Data Setup before RCLK
Receive Data Hold after RCLK
RFS Delay after RCLK (Internally Generated RFS)
RFS Hold after RCLK (Internally Generated RFS)
TFS Delay after TCLK (Internally Generated TFS)
TFS Hold after TCLK (Internally Generated TFS)
Transmit Data Delay after TCLK
Transmit Data Hold after TCLK
TFS Delay after TCLK (Internally Generated TFS)
TFS Hold after TCLK (Internally Generated TFS)
Transmit Data Delay after TCLK
Transmit Data Hold after TCLK
TCLK/RCLK Width
Data Enable from External TCLK
Data Disable from External TCLK
Data Enable from Internal TCLK
Data Disable from Internal TCLK
TCLK/RCLK Delay from CLKIN
SPORT Disable after CLKIN
TFS Setup before CLKIN
TFS Hold after CLKIN
1
; RFS Setup before RCLK
1
1
1, 2
1, 2
3
3
3
3
3
3
3
1
1
3
1
3
3
3
3
3
1
3
Rev. B | Page 23 of 48
Min
4
4.5
2
4.5
9.5
t
9.5
1
4.5
3
2.5
3
5
−1.5
−0.5
(SCLK/2) − 2
3.5
−0.5
5.5
(TCK/2) + 0.5
CK
5 V
Max
14.5
14.5
17.5
5
7.5
(SCLK/2) + 2
12
3
23.5 + 3 DT/8
18.5
Min
4
4.5
2
4.5
9.5
t
9.5
1
4.5
3
2.5
3
5
−1.5
−0.5
(SCLK/2) − 2.5
4
−0.5
5.5
(TCK/2) + 0.5
CK
AD14060/AD14060L
3.3 V
Max
14.5
14.5
17.5
5
7.5
(SCLK/2) + 2.5
12
3
23.5 + 3 DT/8
18.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns