AD14060BF-4 Analog Devices Inc, AD14060BF-4 Datasheet - Page 8

• Manufacturer Part Number: AD14060BF-4
• Description: IC DSP CMOS 32BIT 308CQFP
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of AD14060BF-4

• Rohs Status: RoHS non-compliant
• Interface: Host Interface, Link Port, Serial Port
• Clock Rate: 40MHz
• Non-volatile Memory: External
• On-chip Ram: 2MB
• Voltage - I/o: 5.00V
• Voltage - Core: 5.00V
• Operating Temperature: -40°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 308-CQFP
• Device Core Size: 32b
• Architecture: Enhanced Harvard
• Clock Freq (max): 40MHz
• Mips: 40
• Device Input Clock Speed: 40MHz
• Ram Size: 1.9073535156MB
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 308
• Package Type: CQFP
• Lead Free Status / Rohs Status: Not Compliant

AD14060/AD14060L
MEMORY READ—BUS MASTER
Use these specifications for asynchronous interfacing to memories (and memory-mapped peripherals) without reference to CLKIN.
These specifications apply when the AD14060/AD14060L is the bus master accessing external memory space.
These switching characteristics also apply for bus master synchronous read/write timing (see the Synchronous Read/Write—Bus Master
section). If these timing requirements are met, the synchronous read/write timing can be ignored (and vice versa).
Table 8. Specifications
Parameter
Timing Requirements:
t
t
t
t
t
t
Switching Characteristics:
t
t
t
t
t
W = number of wait states specified in WAIT register × t
HI = t
H = t
1
2
3
4
DAD
DRLD
HDA
HDRH
DAAK
DSAK
DRHA
DARL
RW
RWR
SADADC
Data delay/setup: User must meet t
For MS x, SW , BMS , the falling edge is referenced.
Data hold: User must meet t
capacitive and dc loads.
ACK delay/setup: User must meet t
CK
CK
, if an address hold cycle occurs as specified in WAIT register; otherwise, H = 0.
, if an address hold cycle or bus idle cycle occurs, as specified in WAIT register; otherwise, HI = 0.
WR, DMAG
ADDRESS
Address, Delay to Data Valid
RD Low to Data Valid
Data Hold from Address
Data Hold from RD High
ACK Delay from Address
ACK Delay from RD Low
Address Hold after RD High
Address to RD Low
RD Pulse Width
RD High to WR, RD, DMAGx Low
Address Setup before ADRCLK High
MSx, SW
ADRCLK
DATA
(OUT)
BMS
ACK
RD
HDA
, t
HDRH
2
DSAK
t
DAD
SADADC
, or synchronous specification, t
1
, t
, t
DRLD
DAAK
4
3
3
2, 4
t
DARL
, or synchronous specification, t
, or synchronous specification, t
1, 2
t
DAAK
CK
2
.
t
t
DAD
DSAK
Min
1
2.5
−0.5 + H
1.5 + 3 DT/8
12.5 + 5 DT/8 + W
8 + 3 DT/8 + HI
−0.5 + DT/4
Figure 7. Memory Read—Bus Master
HDATI
t
DRLD
. See the
Rev. B | Page 8 of 48
SSDATI
SACKC
.
.
System Hold Time Calculation Example
5 V
Max
17.5 + DT + W
11.5 + 5 DT/8 + W
13.5 + 7 DT/8 + W
7.5 + DT/2 + W
t
RW
Min
1
2.5
−0.5 + H
1.5 + 3 DT/8
12.5 + 5 DT/8 + W
8 + 3 DT/8 + HI
−0.5 + DT/4
section for the calculation of hold times given
t
HDRH
t
HDA
t
3.3 V
DRHA
t
RWR
17.5 + DT + W
11.5 + 5 DT/8 + W
13.5 + 7 DT/8 + W
7.5 + DT/2 + W
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns