EP3C25E144I7N Altera, EP3C25E144I7N Datasheet - Page 31

• Manufacturer Part Number: EP3C25E144I7N
• Description: IC CYCLONE III FPGA 25K 144 EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C25E144I7N

• Number Of Logic Elements/cells: 24624
• Number Of Labs/clbs: 1539
• Total Ram Bits: 608256
• Number Of I /o: 82
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 144-EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.544-2370 - KIT STARTER CYCLONE III EP3C25
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2542

Design and Compilation
© November 2008 Altera Corporation
f
Figure 3. Synchronous Design
If the combinational logic output from your design feeds to another part of the design,
have the signal go through a register, as illustrated in
using the combinational logic output as a clock signal or as an asynchronous reset
signal. Due to propagation delays through the combinational logic, the signal may go
through a number of transitions before the output settles to a new value. This means
changes to the combinational output can trigger a period of instability.
As the input of the register is only sampled and transferred to the design (for
example, the combinational logic 2 shown in
clock, transitions taking place on data inputs of the register do not affect the register
output or input to the other part of the design until the next active clock edge. As long
as the setup and hold time of the register is not violated, the register effectively
isolates any glitches or instable input signals from other logics.
Figure 4. Registering Combinational Output Signal
It is recommended that you register the input signals to the device as well to filter out
any glitches. The Cyclone III I/Os have input registers for this purpose. Using the
input registers for your input signals allows faster setup times compared to using the
LE registers. This can be done with the Fast Input Register assignment.
Also, your design should not rely on delay paths within the architecture of a device,
for example using the LCELL primitives to increase the delay of certain signals in the
design because factors such as temperature, voltage, process change, or placement
and routing change could affect the timing of logic paths in the device. Any change in
timing to a specific path could cause unwanted functional changes and affect the
design functionality. Synchronization eliminates the unwanted functional changes.
For more information about synchronizing your design, refer to the
Recommendations for Altera Devices and the Quartus II Design Assistant
volume 1 of the Quartus II Handbook or the Quartus II Help.
Combinational
clock
Logic 1
clock
D
Q
D
Q
Figure
D
Combinational
4) on every active edge of the
Table
Logic 2
Q
4. This applies if you are
Design
chapter in
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