EP3C10F256C8N Altera, EP3C10F256C8N Datasheet - Page 137

• Manufacturer Part Number: EP3C10F256C8N
• Description: IC CYCLONE III FPGA 10K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C10F256C8N

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 182
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of Logic Blocks: 645
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2417; EP3C10F256C8N

Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
High-Speed I/O Standards Support
Figure 7–9. LVPECL DC-Coupled Termination
Differential SSTL I/O Standard Support in the Cyclone III Device Family
Figure 7–10. Differential SSTL Class I Interface
© December 2009
Output Buffer
f
Altera Corporation
LVPECL Transmitter
Figure 7–9
The differential SSTL I/O standard is a memory-bus standard used for applications
such as high-speed DDR SDRAM interfaces. The Cyclone III device family supports
differential SSTL-2 and SSTL-18 I/O standards. The differential SSTL I/O standard
requires two differential inputs with an external reference voltage (VREF) as well as an
external termination voltage (VTT) of 0.5 × V
connected. The differential SSTL output standard is only supported at PLL#_CLKOUT
pins using two single-ended SSTL output buffers (PLL#_CLKOUTp and
PLL#_CLKOUTn), with the second output programmed to have opposite polarity. The
differential SSTL input standard is supported on the GCLK pins only, treating
differential inputs as two single-ended SSTL and only decoding one of them.
For more information about the differential SSTL electrical specifications, refer to the
Cyclone III Device I/O Features
Cyclone III LS Device Data Sheet
Figure 7–10
shows the LVPECL DC-coupled termination.
shows the differential SSTL Class I interface.
50
50
chapter and the
chapters.
V
100
TT
CCIO
Cyclone III Device Data Sheet
Cyclone III Device Family
to which termination resistors are
LVPECL Receiver
V
TT
Cyclone III Device Handbook, Volume 1
Receiver
and
7–13