EP3C10F256C8N Altera, EP3C10F256C8N Datasheet - Page 170

• Manufacturer Part Number: EP3C10F256C8N
• Description: IC CYCLONE III FPGA 10K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C10F256C8N

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 182
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of Logic Blocks: 645
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2417; EP3C10F256C8N

9–10
Configuration Scheme
Cyclone III Device Handbook, Volume 1
1
the Enable user supplied start-up clock option (CLKUSR) option, the CLKUSR pin is
the initialization clock source. Supplying a clock on the CLKUSR pin does not affect
the configuration process. After the configuration data is accepted and CONF_DONE
goes high, the Cyclone III device family requires a certain amount of clock cycles to
initialize and to enter user mode.
Table 9–5
family.
Table 9–5. Initialization Clock Cycles Required in Cyclone III Device Family
Table 9–6
Table 9–6. Maximum CLKUSR Frequency for Cyclone III Device Family
If you use the optional CLKUSR pin and the nCONFIG pin is pulled low to restart
configuration during device initialization, ensure that the CLKUSR pin continues to
toggle when nSTATUS is low (a maximum of 230 μs).
User Mode
An optional INIT_DONE pin is available that signals the end of initialization and the
start of user mode with a low-to-high transition. The Enable INIT_DONE Output
option is available in the Quartus II software from the General tab of the Device and
Pin Options dialog box. If you use the INIT_DONE pin, it is high due to an external
10-kΩ pull-up resistor when nCONFIG is low and during the beginning of
configuration. After the option bit to enable INIT_DONE is programmed into the
device (during the first frame of configuration data), the INIT_DONE pin goes low.
When initialization is complete, the INIT_DONE pin is released and pulled high. This
low-to-high transition signals that the device has entered user mode. In user mode,
the user I/O pins function as assigned in your design and no longer have weak
pull-up resistors.
A configuration scheme with different configuration voltage standards is selected by
driving the MSEL pins either high or low, as listed in
The MSEL pins are powered by V
pull-down resistors that are always active.
Cyclone III LS
Cyclone III LS
Cyclone III
Cyclone III
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Device
Device
lists the required clock cycles for proper initialization in Cyclone III device
lists the maximum CLKUSR frequency (f
CCINT
. The MSEL[3..0] pins have 9-kΩ internal
Initialization Clock Cycles
f
MAX
MAX
3,185
3,192
133
100
(MHz)
Table
) for Cyclone III device family.
© December 2009 Altera Corporation
9–7.
Configuration Features