EP3C10F256C8N Altera, EP3C10F256C8N Datasheet - Page 54

• Manufacturer Part Number: EP3C10F256C8N
• Description: IC CYCLONE III FPGA 10K 256-FBGA
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C10F256C8N

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 423936
• Number Of I /o: 182
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 256-FBGA
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 182
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: FBGA
• No. Of Logic Blocks: 645
• Family Type: Cyclone III
• No. Of I/o's: 182
• I/o Supply Voltage: 3.3V
• Operating Frequency Max: 402MHz
• Operating Temperature Range: 0°C To +85°C
• Rohs Compliant: Yes
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2417; EP3C10F256C8N

3–18
Figure 3–17. Mixed Port Read-During-Write: Old Data Mode
Conflict Resolution
Cyclone III Device Handbook, Volume 1
f
q_b (asynch)
1
address_b
address_a
clk_a&b
wren_a
rden_b
data_a
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode, which has one port
reading and the other port writing to the same address location with the same clock.
In this mode, you also have two output choices: Old Data mode or Don't Care mode.
In Old Data mode, a read-during-write operation to different ports causes the RAM
outputs to reflect the old data at that address location. In Don't Care mode, the same
operation results in a “Don't Care” or unknown value on the RAM outputs.
For more information about how to implement the desired behavior, refer to the
Megafunction User
Figure 3–17
behavior for the Old Data mode. In Don't Care mode, the old data is replaced with
“Don't Care”.
For mixed-port read-during-write operation with dual clocks, the relationship
between the clocks determines the output behavior of the memory. If you use the
same clock for the two clocks, the output is the old data from the address location.
However, if you use different clocks, the output is unknown during the mixed-port
read-during-write operation. This unknown value may be the old or new data at the
address location, depending on whether the read happens before or after the write.
When you are using M9K memory blocks in true dual-port mode, it is possible to
attempt two write operations to the same memory location (address). Because there is
no conflict resolution circuitry built into M9K memory blocks, this results in
unknown data being written to that location. Therefore, you must implement
conflict-resolution logic external to the M9K memory block.
A
shows a sample functional waveform of mixed port read-during-write
a (old data)
a
a
Guide.
B
A
C
B
D
b (old data)
Chapter 3: Memory Blocks in the Cyclone III Device Family
E
b
b
D
F
© December 2009 Altera Corporation
E
Design Considerations
RAM