EP2SGX130GF1508I4N Altera, EP2SGX130GF1508I4N Datasheet - Page 43

• Manufacturer Part Number: EP2SGX130GF1508I4N
• Description: IC STRATIX II GX 130K 1508-FBGA
• Manufacturer: Altera
• Series: Stratix® II GXr

Specifications of EP2SGX130GF1508I4N

• Number Of Logic Elements/cells: 132540
• Number Of Labs/clbs: 6627
• Total Ram Bits: 6747840
• Number Of I /o: 734
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1508-FBGA
• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 132540
• # I/os (max): 734
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 132540
• Ram Bits: 6747840
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1508
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2175

Altera Corporation
October 2007
Transceiver Clocking
Each Stratix II GX device transceiver block contains two transmitter PLLs
and four receiver PLLs. These PLLs can be driven by either of the two
reference clocks per transceiver block. These REFCLK signals can drive all
global clocks, transmitter PLL inputs, and all receiver PLL inputs.
Subsequently, the transmitter PLL output can only drive global clock
lines and the receiver PLL reference clock port. Only one of the two
reference clocks in a quad can drive the Inter Quad (I/Q) lines to clock the
PLLs in the other quads.
Figure 2–29
global clock connections for the EP2SGX130 device.
shows the inter-transceiver line connections as well as the
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
2–35