XC4VFX100-10FFG1517I Xilinx Inc, XC4VFX100-10FFG1517I Datasheet - Page 348

• Manufacturer Part Number: XC4VFX100-10FFG1517I
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517I

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
348
The circuitry that results from instantiating the IDELAYCTRL components is shown in
Figure
Instantiating IDELAYCTRL with and without LOC Constraints
There are cases where the user instantiates an IDELAYCTRL module with a LOC
constraint but also instantiates an IDELAYCTRL module without a LOC constraint. In the
case where an IP Core is instantiated with a non-location constrained IDELAYCTRL
module and also wants to instantiate an IDELAYCTRL module without a LOC constraint
for another part of the design, the implementation tools will perform the following:
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INST "dlyctrl_2" LOC=IDELAYCTRL_X0Y1;
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INST "dlyctrl_n" LOC=IDELAYCTRL_XnYn;
Instantiate the LOC IDELAYCTRL instances as described in the section
IDELAYCTRL with Location (LOC)
Replicate the non-location constrained IDELAYCTRL instance to populate with an
IDELAYCTRL instance in every clock region without a location constrained
IDELAYCTRL instance in place.
The signals connected to the RST and REFCLK input ports of the non-location
constrained IDELAYCTRL instance are connected to the corresponding input ports of
the replicated IDELAYCTRL instances.
If the RDY port of the non-location constrained IDELAYCTRL instance is ignored,
then all the RDY signals of the replicated IDELAYCTRL instances are also ignored.
If the RDY port of the non-location constrained IDELAYCTRL instance is connected,
then the RDY port of the non-location constrained instance plus the RDY ports of the
replicated instances are connected to an auto-generated AND gate. The
implementation tools assign the signal name connected to the RDY port of the non-
location constrained instance to the output of the AND gate.
All the ports of the location constrained instances (RST, REFCLK, and RDY) are
independent from each other and from the replicated instances.
7-18.
Figure 7-18: Instantiate IDELAYCTRL with LOC Constraint
REFCLK
www.xilinx.com
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rst_1
rst_2
rst_n
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REFCLK
RST
REFCLK
RST
REFCLK
RST
IDELAYCTRL_1
IDELAYCTRL_2
IDELAYCTRL_n
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RDY
RDY
RDY
UG070 (v2.6) December 1, 2008
ug070_7_18_080104
Virtex-4 FPGA User Guide
rdy_1
rdy_2
rdy_n
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Instantiating
R