XC4VFX100-10FFG1517I Xilinx Inc, XC4VFX100-10FFG1517I Datasheet - Page 75

• Manufacturer Part Number: XC4VFX100-10FFG1517I
• Description: IC FPGA VIRTEX-4FX 100K 1517FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX100-10FFG1517I

• Number Of Logic Elements/cells: 94896
• Number Of Labs/clbs: 10544
• Total Ram Bits: 6930432
• Number Of I /o: 768
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 1517-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
Frequency Synthesis
R
Frequency Synthesis Operation
1. This is an asynchronous clock mux as shown in
•
The DCM provides several flexible methods for generating new clock frequencies. Each
method has a different operating frequency range and different AC characteristics. The
CLK2X and CLK2X180 outputs double the clock frequency. The CLKDV output provides a
divided output clock (lower frequency) with division options of 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5,
5.5, 6, 6.5, 7, 7.5, 8, 9, 10, 11, 12, 13, 14, 15, and 16.
The DCM also offers fully digital, dedicated frequency-synthesizer outputs CLKFX and its
opposite phase CLKFX180. The output frequency can be any function of the input clock
frequency described by M ÷ D, where M is the multiplier (numerator) and D is the divisor
(denominator).
The frequency synthesized outputs can drive the global-clock routing networks within the
device. The well-buffered global-clock distribution network minimizes clock skew due to
differences in distance or loading.
The DCM clock output CLKFX is any M ÷ D factor of the clock input to the DCM.
Specifications for M and D, as well as input and output frequency ranges for the frequency
synthesizer, are provided in the
Only when feedback is provided to the CLKFB input of the DCM is the frequency
synthesizer output phase aligned to the clock output, CLK0.
The internal operation of the frequency synthesizer is complex and beyond the scope of
this document. As long as the frequency synthesizer is within the range specified in the
CLKIN
Reset
while acquiring LOCK the CLKIN clock feeds DCM2. After the DCM1 locks the
DCM1 output clock feeds DCM2. DCM2 is held in reset for 16 additional CLKIN
cycles.
It is recommended that R1 > R2, where:
The ranges of M and D values are given in the data sheet.
R1 =
R2 =
Figure 2-5
CLKIN
CLKFB
RST
M/D ratio for DCM1
M/D ratio for DCM2
DCM1
BUFG
illustrates this approach.
LOCKED
CLKDV
CLK0
www.xilinx.com
Figure 2-5: Cascading DCMs
Virtex-4 Data
BUFCTRL
INV
I0
I1
S
Note (1)
D
CLK
Figure 1-13, page
SRL16
Sheet.
Q
CLKIN
CLKFB
RST
36.
DCM2
BUFG
DCM Design Guidelines
LOCKED
CLKFX
CLK0
BUFG
UG070_02_23_031308
CLKFX
LOCK
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