XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 313

• Manufacturer Part Number: XC5VFX30T-1FF665CES
• Description: IC FPGA VIRTEX5FX 30K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FF665CES

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Number Of Gates: -

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
•
•
When the electrical characteristics of a design differ from the nominal values, the system
SSO limit changes. The degree of difference determines the new effective limit for the
design. A figure called “SSO Allowance” is used as a single derating factor, taking into
account the combined effect of all three groups of system electrical characteristics.
The SSO allowance is a number ranging from 0 to 100% and is a product of three scaling
factors:
The First Scaling Factor accounts for the PCB PDS parasitic inductance. It is determined by
dividing the nominal PCB PDS inductance by the user's PCB PDS inductance, L
The PCB PDS inductance is determined based on a set of board geometries: board
thickness, via diameter, breakout trace width and length, and any other additional
structures including sockets.
The Second Scaling Factor accounts for the maximum allowable power system disturbance.
It is determined by dividing the user's maximum allowable power system disturbance,
(V
V
voltage and input logic low threshold.
The Third Scaling Factor accounts for the capacitive loading of outputs driven by the FPGA.
It is based on the transient current impact of every additional picofarad of load capacitance
above the assumed nominal. For every additional 1 pF of load capacitance over the
nominal, approximately 9 mV of additional power system disturbance will occur. The
additional power system disturbance is compared to the nominal power system
disturbance, and a scale factor is derived from the relationship. C
average load capacitance.
Example calculations show how each scale factor is computed, as well as the SSO
allowance. The system parameters used in this example are:
First Scaling Factor (SF1)
Second Scaling Factor (SF2)
Third Scaling Factor (SF3)
= V
= 600 mV/((22 pF – 15 pF) × 9 mV/pF) + 600 mV
= 600 mV/663 mV
= 0.905
DISTURBANCE_USER
DISTURBANCE_USER
DISTURBANCE_NOM
Maximum allowable power system disturbance voltage (nominal 600 mV)
Capacitive loading (nominal 10 pF per load)
L
V
C
PDS_USER
DISTURBANCE_USER
LOAD_USER
is usually determined by taking the lesser of input undershoot
) by the nominal maximum power system disturbance.
/((C
www.xilinx.com
LOAD_USER
= 1.1 nH
= 550 mV
= 22 pF
= L
= 1.0 nH/1.1 nH
= 0.909
= V
= 550 mV/600 mV
= 0.917
PDS_NOM
DISTURBANCE_USER
– C
LOAD_NOM
/L
PDS_USER
Simultaneous Switching Output Limits
) × 9 mV/pF) + V
/V
DISTURBANCE_NOM
LOAD_USER
DISTURBANCE_NOM
is the user's
PDS_USR
313
.