XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 355

• Manufacturer Part Number: XC5VFX30T-1FF665CES
• Description: IC FPGA VIRTEX5FX 30K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FF665CES

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Number Of Gates: -

Table 8-1: ISERDES_NODELAY Port List and Definitions
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Q1 – Q6
SHIFTOUT1
SHIFTOUT2
BITSLIP
CE1
CE2
CLK
CLKB
CLKDIV
D
OCLK
SHIFTIN1
SHIFTIN2
RST
Port Name
ISERDES_NODELAY Ports
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Registered Outputs - Q1 to Q6
Table 8-1
The output ports Q1 to Q6 are the registered outputs of the ISERDES_NODELAY module.
One ISERDES_NODELAY block can support up to six bits (i.e., a 1:6 deserialization). Bit
widths greater than six (up to 10) can be supported. See
first data bit received appears on the highest order Q output.
The bit ordering at the input of an OSERDES is the opposite of the bit ordering at the
output of an ISERDES_NODELAY block, as shown in
significant bit A of the word FEDCBA is placed at the D1 input of an OSERDES, but the
same bit A emerges from the ISERDES_NODELAY block at the Q6 output. In other words,
D1 is the least significant input to the OSERDES, while Q6 is the least significant output of
the ISERDES_NODELAY block. When width expansion is used, D1 of the master
OSERDES is the least significant input, while Q4 of the slave ISERDES_NODELAY block is
the least significant output.
1 (each)
1 (each)
Width
1
1
1
1
1
1
1
1
1
1
1
lists the available ports in the ISERDES_NODELAY primitive.
Registered outputs. See
Carry out for data width expansion. Connect to SHIFTIN1 of slave IOB. See
ISERDES Width
Carry out for data width expansion. Connect to SHIFTIN2 of slave IOB. See
ISERDES Width
Invokes the Bitslip operation. See
Clock enable inputs. See
High-speed clock input. Clocks serial input data stream. See
Input -
High-speed secondary clock input. Clocks serial input data stream. Always
connect this CLK.
Divided clock input. Clocks delay element, deserialized data, Bitslip submodule,
and CE unit. See
Serial input data from IOB. See
High-speed clock input for memory applications. See
Strobe-Based Memory Interfaces -
Carry input for data width expansion. Connect to SHIFTOUT1 of master IOB. See
ISERDES Width
Carry input for data width expansion. Connect to SHIFTOUT2 of master IOB. See
ISERDES Width
Active High reset. See
CLK.
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Expansion.
Expansion.
Expansion.
Expansion.
Divided Clock Input -
Reset Input -
Input Serial-to-Parallel Logic Resources (ISERDES)
Registered Outputs - Q1 to
Clock Enable Inputs - CE1 and
Serial Input Data from IOB -
Bitslip Operation -
Description
OCLK.
RST.
CLKDIV.
Figure
ISERDES Width
Q6.
8-3. For example, the least
BITSLIP.
High-Speed Clock for
CE2.
D.
High-Speed Clock
Expansion. The
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