XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 332

• Manufacturer Part Number: XC5VFX30T-1FF665CES
• Description: IC FPGA VIRTEX5FX 30K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FF665CES

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Number Of Gates: -

Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-10
332
Figure 7-10: Basic Sections of Blocks Related to IODELAY Turnaround with Pertinent Paths Shown
CLK
CLK
Q1
Q2
D1
D2
T1
T2
IODELAY Turnaround Time Usage Model
ODDR
ODDR
IDDR
When using IODELAY in bidirectional mode, the turnaround time needs to be considered.
Figure 7-10
that applies to one use of the bidirectional IODELAY functionality.
When DELAY_SRC = IO, MUXE and MUXF dynamically selects ODATAIN or IDATAIN
and ODELAY_VALUE or IDELAY_VALUE inside the IODELAY block.
The following Verilog code segment is used for demonstrating bidirectional IODELAY:
IDDR #(
)IDDR_INST (
);
IOBUF #(
)IOBUF_INST (
);
.DDR_CLK_EDGE ("SAME_EDGE"),
.INIT_Q1 (1'b0),
.INIT_Q2 (1'b0),
.SRTYPE ("SYNC")
.C(clk),
.CE(1'b1),
.D(DATAOUT),
.R(1'b0),
.S(1'b0),
.Q1(Q1),
.Q2(Q2)
.IOSTANDARD ("LVCMOS25")
.I(DATAOUT),
.T(TSCONTROL),
.O(IDATAIN),
.IO(IOPAD_DATA)
shows a simplified block diagram of the IODELAY in the Virtex-5 FPGA IOB
DATAOUT
ODATAIN
IODELAY
Delay
Chain
www.xilinx.com
TSCONTROL
MUX E
MUX F
T
ODELAY_VALUE
IDELAY_VALUE
ODATAIN
IDATAIN
OBUF
IBUF
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
IOB
IODELAY_01_081407
PAD