XC5VFX30T-1FF665CES Xilinx Inc, XC5VFX30T-1FF665CES Datasheet - Page 46

• Manufacturer Part Number: XC5VFX30T-1FF665CES
• Description: IC FPGA VIRTEX5FX 30K 665FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 FXTr

Specifications of XC5VFX30T-1FF665CES

• Number Of Logic Elements/cells: 32768
• Number Of Labs/clbs: 2560
• Total Ram Bits: 2506752
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Number Of Gates: -

Chapter 1: Clock Resources
VHDL and Verilog Templates
46
Regional Clock Nets
In addition to global clock trees and nets, Virtex-5 devices contain regional clock nets.
These clock trees are also designed for low-skew and low-power operation. Unused
branches are disconnected. The clock trees also manage the load/fanout when all the logic
resources are used.
Regional clock nets do not propagate throughout the whole Virtex-5 device. Instead, they
are limited to only one clock region. One clock region contains four independent regional
clock nets.
To access regional clock nets, BUFRs must be instantiated. A BUFR can drive regional
clocks in up to two adjacent clock regions
can only access one adjacent region; below or above respectively. The left side BUFRs can
feed the center column I/Os.
X-Ref Target - Figure 1-23
The VHDL and Verilog code for all clocking resource primitives and ISE language
templates are available in the Libraries Guide.
BUFRs
Figure 1-23: BUFR Driving Multiple Regions
www.xilinx.com
(Figure
1-23). BUFRs in the top or bottom region
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
ug190_1_23_012306