Z9025106PSG Zilog, Z9025106PSG Datasheet - Page 20

• Manufacturer Part Number: Z9025106PSG
• Description: IC 32K 8BIT DTC OTP 42-DIP
• Manufacturer: Zilog

Specifications of Z9025106PSG

• Applications: TV Controller
• Core Processor: Z8
• Program Memory Type: OTP (32 kB)
• Controller Series: Digital Television Controller (DTC)
• Ram Size: 300 x 8
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 27
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 42-DIP (0.600", 15.24mm)
• Processor Series: Z902x
• Core: Z8
• Data Bus Width: 8 bit
• Program Memory Size: 32 KB
• Data Ram Size: 300 B
• Interface Type: I2C
• Maximum Clock Frequency: 6 MHz
• Number Of Programmable I/os: 27
• Mounting Style: Through Hole
• On-chip Adc: 4 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Working Register
Group Pointer
x = undefined
%00
%F0
%FF
%7F
%0F
D7 D6 D5 D4 D3 D2 D1 D0
Z8 Register File
Figure 5
Register Pointer
Reserved Expanded
Register
Register File Map
Expanded Register
Bank Pointer
(7)
(6)
(5)
(4)
(C)
(B)
(A)
32 KB Television Controller with OSD
Expanded
Register
Register
Register
%FF
%FE
%FD
%FC
%FB
%FA
%F9
%F8
%F7
%F6
%F5
%F4
%F3
%F2
%F1
%F0
%(F)0F WDTMR
%(F)0E Reserved
%(F)0D Reserved
%(F)0C Reserved
%(F)0B SMR
%(F)0A Reserved
%(F)09 PWM6H
%(F)08 PWM6L
%(F)07 MC_Reg
%(F)06 MR_En
%(F)05 MC_End
%(F)04 MC_St
%(F)03 PRT6_DTA
%(F)02 PRT6_DRT
%(F)01 4ADC_DTA
%(F)00 PCON
%(0)03 Reserved
%(0)02 P2
%(0)01 Reserved
%(0)00 Reserved
IPR
P01M
P2CNTL
P2M
PRE0
T0
PRE1
T1
TMR
Reserved
SPL
SPH
IMR
IRQ
RP
FLAGS
Reset Condition
Reset Condition
D7 D6 D5 D4 D3 D2 D1 D0
x
x
0
x
0
0
x
1
0
1
x
x
x
x
0
x
0
0
0
x
x
1
1
0
1
x
x
0
Register Bank (F)
Reset Condition
x
x
0
x
x
0
x
1
0
1
x
x
x
x
0
x
0
0
0
x
x
1
1
0
1
x
x
0
x
x
0
x
x
0
x
1
0
1
x
x
x
x
0
x
1
0
0
x
x
1
1
0
1
x
0
0
PS001301-0800
0
0
x
x
0
x
x
0
x
1
0
1
x
x
x
x
0
x
0
0
0
0
1
1
0
1
x
0
x
x
0
x
x
0
1
0
1
x
x
x
x
0
x
0
0
0
0
1
1
x
1
x
0
0
0
x
x
x
0
x
x
0
x
1
0
1
x
x
x
x
0
1
0
0
0
0
0
1
1
x
1
x
0
0
0
0
x
x
0
x
x
0
x
1
0
1
x
x
0
x
0
x
0
0
0
0
0
1
1
x
1
x
x
x
0
x
x
0
x
1
1
1
0
x
0
x
0
x
0
0
0
0
0
1
1
x
0
x
0
0
12