SL811S Cypress Semiconductor Corp, SL811S Datasheet - Page 12

• Manufacturer Part Number: SL811S
• Description: IC USB SLAVE CTRLR 28PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811S

• Applications: USB Host/Slave Controller
• Controller Series: USB-Hosts
• Ram Size: 256 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Core Processor: -
• Program Memory Type: -
• Other names: 428-1460

5.4
The USB Control registers manage communication and data flow on the USB. Each USB device is composed of a collection of
independently operating endpoints. Each endpoint has a unique identifier, which is the Endpoint Number. For more details about
USB endpoints, please refer to the USB Specification 1.1, Section 5.3.1.
The control and status registers are mapped as follows:
5.4.1
The Control Register enables/disables USB transfers and DMA Operations with control bits.
Bit 0 should be set to ‘1’ to enable USB communication. The default is zero on power up.
Bit 1 is a DMA
Bit 2 sets the direction for DMA transfer.
Bits 3 – 4. The J-K force state control bits can be used to generate various USB bus conditions. Forcing K-state can be used for
Peripheral device remote wake-up, Resume and other modes. These two bits are set to zero on power up.
Document #: 38-08009 Rev. **
Control Register
Interrupt Enable Register
USB Address Register
Interrupt Status Register
Current Data Set Register
SOF Low Byte Register
SOF High Byte Register
DMA Total Count Low Byte Register
DMA Total Count High Byte Register
Bit Position
0
1
2
3
4
5
6
7
USB Control Registers
Control Register, Address [05H]
enable
DMA Enable
USB Enable
Bit Name
Reserved
DMA Dir
bit. DMA is initiated when DMA Count High is written.
STBYD
SPSEL
J-K0
J-K1
Register Name
Overall Enable for transfers. '1' enables, '0' disables.
Enable DMA Operation when ‘1’. Disable = ‘0’.
DMA transfer direction bit. Set ‘1’ for DMA read cycles from SL811S, Set ‘0’ for DMA
write cycles.
J-K Force State Bit 0. [See Force State Table]
J-K Force State Bit 1.
Speed Select. ‘0’ select FS. ‘1’ select LS
XCVR Power control. ‘1’ sets XCVR to low power. Normally ‘0’. Suspend mode is entered
if Bit 6 is set = ‘1’ and Bit 0 (USB Enable) is set = ‘0’.
Reserved bit - must be set to '0'.
Function
Address (in Hex)
0D h
0E h
05 h
06 h
07 h
15 h
16 h
35 h
36 h
SL811S/T
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