MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet - Page 47

• Manufacturer Part Number: MPC180LMB
• Description: IC SECURITY PROCES 66MHZ 100LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MPC180LMB

• Processor Type: Security Processor
• Speed: 66MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bits
0–19
20
21
22
23
24
25
26
27
28
29
30
31
Name
—
ENGO Enables automatic start of hashing as soon as the MDMB buffers have all been written. It
OPAD
IPAD
—
MD5
MD4
RST
IE
GO
BSWP The BSWP bit causes byte-swapping of the Message Digest Buffer Registers
STEP
—
Reserved, should be cleared.
is not necessary to set the GO bit manually.
The assertion of OPAD causes:
1. The value written to the 512 bit Message Buffer to be exclusive-ORed with the outer
hash pad value
2. Unlike IPAD, a procedural change occurs: upon starting the hash of the value written to
the Message Buffer, the contents of the Message Digest Buffer is copied to the Message
Buffer, and is padded appropriately.
By performing the copy from MDB to MB, the step of appending the inner hash result to
the padded key is performed automatically. OPAD is autocleared upon completion of a
hash of a single message block.
The assertion of IPAD causes the value written to the 512 bit Message Buffer to be
exclusive-ORed with the inner hash pad value. This value is autocleared upon completion
of a hash of a single message block. Note that because this control bit affects the value
stored in the 512 bit message buffer, if block chaining is to be used, it should be set only
while the secret key is written to the 512 bit Message Buffer, and should be cleared
manually at the same time GO is asserted.
Reserved, should be cleared.
and MD5 are not asserted, a SHA-1 Hash will be computed.
and MD5 are not asserted, a SHA-1 Hash will be computed.
The RST bit is a software reset signal. When activated, the MDEU will reset immediately,
halting any ongoing hash. All registers and buffers revert to their initial state. Normally,
asserting GO continues an existing hash function across multiple 512-bit message
blocks. Should a fresh-hash be desired for a new message block, the RST bit should be
asserted prior to loading the new message block into the Message Buffer.
The IE bit represents the Interrupt Enable flag. When set to 1, the IRQ signal is enabled,
thus when an interrupt occurs, the IRQ signal will be activated. When the IE bit is set to 0,
all interrupts are disabled, and the IRQ output pin will be held inactive, that is, 0. The IE
bit acts as the global interrupt enable.
The GO bit initiates the processing of the 512 bit message currently stored in the
Message Buffer. This hash will be a continuation of any existing hash of multiple
message blocks. In order to begin a new hash, the RST bit described below should be
asserted prior to loading the new 512 bit Message Block. The 512 bit Message Block is
double-buffered; a new block of message may be written while a hash is under process. If
a new block is so written, then hashing will continue with the new block without GO
needing to be reasserted.
(MDA-MDE) as they are read out of the MDEU.
The STEP bit allows the MDEU to be stepped through on a single clock cycle basis.
When active, that is 1, the MDEU computes one “round” of the currently selected hash.
Reserved, should be cleared.
The assertion of the MD5 bit signifies that an MD5 hash will be computed. If both MD4
The assertion of the MD4 bit signifies that an MD4 hash will be computed. If both MD4
Freescale Semiconductor, Inc.
Chapter 6. Message Digest Execution Unit
For More Information On This Product,
Table 6-2. MCR Field Descriptions
Go to: www.freescale.com
Description
Operational Registers
6-3