MPC180LMB Freescale Semiconductor, MPC180LMB Datasheet - Page 52

• Manufacturer Part Number: MPC180LMB
• Description: IC SECURITY PROCES 66MHZ 100LQFP
• Manufacturer: Freescale Semiconductor

Specifications of MPC180LMB

• Processor Type: Security Processor
• Speed: 66MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Bits
0–1
2–3
4–5
6
7
8
Operational Registers
7.1.2 Control Register (PKCR)
The Control Register contains static bits that define the mode of operation for the PKEU.
In addition to the static control bits, several bits are dynamic. These dynamic bits are set by
a write to the PKCR initiated by the host processor, and are reset automatically by the
PKEU after one cycle of operation. All unused bits of the PKCR are read as 0 values.
Figure 7-1 shows the PKEU control register.
Table 7-2 describes the PKEU control register fields.
7-2
Auto clear
Reset
Field
Addr
R/W
Name
regNsel 00 memory N block 0 select
regBsel 00 memory B block 0 select
regAsel 00 memory A block 0 select
—
F
XYZ
2
M
regNsel
0
01 memory N block 1 select
10 memory N block 2 select
11 memory N block 3 select
01 memory B block 1 select
10 memory B block 2 select
11 memory B block 3 select
01 memory A block 1 select
10 memory A block 2 select
11 memory A block 3 select
Reserved, should be cleared.
The F
executing operations for ECC F
This would be required for all RSA and ECC F
0 integer arithmetic (RSA or ECC F
1 polynomial-basis arithmetic (ECC F
The XYZ bit enables the PKEU point multiply operation to bypass certain processing used support
systems that operate in affine coordinates. Specifically, when set, the PKEU simply provides the
final results (i.e. the X, Y, and Z field elements) which are no longer in the Montgomery format.
When XYZ is zero, the PKEU assists the host in achieving its desired affine coordinate results. This
is accomplished by including Z
Montgomery residue system. It is the responsibility of the host to find the inverses of Z
provide these back to the PKEU to compute the affine coordinates.
0 affine coordinates
1 projective coordinates
1
2
M bit causes the PKEU to perform arithmetic in the polynomial-basis. This must be set when
regBsel
2
Figure 7-1. PKEU Control Register (PKCR)
Freescale Semiconductor, Inc.
MPC180LMB Security Processor User’s Manual
Table 7-2. PKCR Field Descriptions
For More Information On This Product,
3
regAsel
4
Go to: www.freescale.com
N
5
2
2
m. When clear, all processing is performed using integer arithmetic.
and Z
The regAsel, regBsel, and regNsel fields set pointers referencing
memory blocks in the A, B, and N memories, respectively. Each
memory, particularly where ECC is concerned, can be thought of
as constituting four sub-memories (e.g. A(0), A(1), A(2), and A(3)).
Each sub-memory contains 32 16-bit locations (or 512 bits). For
ECC processing, these sub-memories are used to store the
multitude of intermediate data and final field elements required
during processing. These memory pointers are used to determine
which memory block is to be referenced during arithmetic
processing or moves from one location to another. All of this is
transparent to the host and performed automatically by the PKEU
for high-level functions. However, for low-level functions, such as
field add or multiplies, the host may set these pointers to reference
a particular memory block. This flexibility allows, for example, the
following computation: A(3) * B(1) * R
—
6
p
)
2
3
M)
in addition to X, Y, and Z and leaving these results in the
F
0000_0000
2
7
M XYZ R
0xB01
Description
R/W
p
processing.
8
p
9
R
n
RST
10
Y
11
IE
N
-1
mod N(2).
GO ECC
12
Y
13
N
2
and Z
14
Y
—
3
15
Y
and