CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 34

• Manufacturer Part Number: CS42L51-CNZ
• Description: IC CODEC STEREO W/HDPN AMP 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZ

• Package / Case: 32-QFP
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 6
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V / 2.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1045

34
4.4
4.4.1
Analog Outputs
AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options
are available, including digital mixes with the ADC signal and an internal Beep Generator. The desired path
to the DAC must be selected using the DATA_SEL[1:0] bits.
Software
Controls:
De-Emphasis Filter
The CODEC includes on-chip digital de-emphasis optimized for a sample rate of 44.1 kHz. The filter re-
sponse is shown in
that utilize 50/15 µs pre-emphasis equalization as a means of noise reduction. De-emphasis is only avail-
able in Single-Speed Mode.
Software
Controls:
Hardware
Control:
DEEMPH
Demph
PCMMIXA_VOL[6:0]
PCMMIXB_VOL[6:0]
MUTE_PCMMIXA
MUTE_PCMMIXB
+12dB/-51.5dB
0.5dB steps
OFFTIME[2:0]
ONTIME[3:0]
“DAC Control (Address 09h)” on page
FREQ[3:0]
REPEAT
SIGNAL PROCESSING ENGINE (SPE)
VOL
BEEP
“DAC Control (Address 09h)” on page
Pin
“DEM” pin 4.
Generator
Beep
Figure
PCMA[1:0]
PCMB[1:0]
Channel
Swap
2.0dB steps
0dB/-50dB
BPVOL[4:0]
14. The de-emphasis feature is included to accommodate audio recordings
VOL
LO
HI
Setting
Figure 13. Output Architecture
OUTA_VOL[7:0]
OUTB_VOL[7:0]
+12dB/-102dB
0.5dB steps
Chnl Vol.
Settings
Σ
DAC_SNGVOL
DAC_SZC[1:0]
DACA_MUTE
DACB_MUTE
INV_DACA
INV_DACB
AMUTE
VOL
58.
58.
BASS_CF[1:0]
TREB_CF[1:0]
TC_EN
Control
Treble/
+12.0dB/-10.5dB
BASS[3:0]
TREB[3:0]
Bass/
1.5dB steps
ARATE[7:0]
RRATE[7:0]
MAX[2:0]
MIN[2:0]
LIM_SRDIS
LIM_ZCDIS
LIMIT_EN
Limiter
Detect
Peak
De-Emphasis Applied
No De-Emphasis
Selection
DATA_SEL[1:0]
01
00
Capacitor DAC
and Filter
Switched
PDN_DACA
PDN_DACB
CHRG_FREQ[3:0]
Headphone
Amp - GND
Centered
Charge
Pump
HP_GAIN[2:0]
CS42L51
DS679F1
Left/Right
HP Out