CS42L51-CNZ Cirrus Logic Inc, CS42L51-CNZ Datasheet - Page 39

• Manufacturer Part Number: CS42L51-CNZ
• Description: IC CODEC STEREO W/HDPN AMP 32QFN
• Manufacturer: Cirrus Logic Inc
• Type: Stereo Audior

Specifications of CS42L51-CNZ

• Package / Case: 32-QFP
• Data Interface: PCM Audio Interface
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• Dynamic Range, Adcs / Dacs (db) Typ: 98 / 98
• Voltage - Supply, Analog: 1.8V, 2.5V
• Voltage - Supply, Digital: 1.8V, 2.5V
• Operating Temperature: -10°C ~ 70°C
• Mounting Type: Surface Mount
• Number Of Adc Inputs: 6
• Number Of Dac Outputs: 2
• Conversion Rate: 96 KSPS
• Interface Type: Serial (2-Wire, 3-Wire, I2C, SPI)
• Resolution: 24 bit
• Operating Supply Voltage: 1.8 V / 2.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 10 C
• Number Of Channels: 2 ADC/2 DAC
• Thd Plus Noise: - 88 dB ADC / - 86 dB DAC
• Peak Reflow Compatible (260 C): No
• Leaded Process Compatible: No
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1005 - BOARD EVAL FOR CS42L51 CODEC
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1045

DS679F1
4.5.1
4.5.2
Slave
LRCK and SCLK are inputs in Slave Mode. The speed of the CODEC is automatically determined based
on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will
then require an internal divide-by-two of MCLK* using either the MCLKDIV2 bit or the MCLKDIV2 stand-
alone control pin.
Additional clock ratios are allowed when the Auto-Detect function is disabled; but the appropriate speed
mode must be selected using the SPEED[1:0] bits.
Master
LRCK and SCLK are internally derived from the internal MCLK (after the divide, if MCLKDIV2 is enabled).
In Hardware Mode the CODEC operates in single-speed only. In Software Mode, the CODEC operates
in either quarter-, half-, single- or double-speed depending on the setting of the SPEED[1:0] bits.
*MCLKDIV2 must be enabled.
Auto-Detect
Mode only)
(Software
Disabled
Enabled
MCLK
512, 768, 1024, 1536,
1024, 1536, 2048*,
2048, 3072
QSM
3072*
÷ 1
÷ 2
Figure 17. Master Mode Timing
MCLKDIV2
0
1
512, 768, 1024*, 1536*
Table 3. MCLK/LRCK Ratios
256, 384, 512, 768,
1024, 1536
HSM
÷ 128
÷ 128
÷ 256
÷ 512
÷ 2
÷ 2
÷ 4
÷ 8
Double
Speed
Quarter
Quarter
Speed
Speed
Speed
Single
Double
Single
Speed
Speed
Speed
Speed
Half
Half
256, 384, 512*, 768*
128, 192, 256, 384,
SPEED[1:0]
00
01
10
11
00
01
10
11
512, 768
SSM
LRCK Output
SCLK Output
(Equal to Fs)
128, 192, 256*, 384*
128, 192, 256, 384
DSM
CS42L51
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