ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 23

• Manufacturer Part Number: ADAU1361BCPZ
• Description: IC CODEC 24B PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1361BCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 7
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
The ADAU1361 is an audio codec that offers high quality audio,
low power, and small package size. The stereo ADC and stereo
DAC each have an SNR of at least +98 dB and a THD + N of
at least −90 dB. The serial data port is compatible with I
justified, right-justified, and TDM modes for interfacing to digital
audio data. The operating voltage range is 1.8 V to 3.65 V, with an
on-board regulator generating the internal digital supply voltage.
The record signal path includes very flexible input configurations
that can accept differential and single-ended analog microphone
inputs as well as a digital microphone input. A microphone bias
pin provides seamless interfacing to electret microphones. Input
configurations can accept up to six single-ended analog signals
or variations of stereo differential or stereo single-ended signals
with two additional auxiliary single-ended inputs. Each input
signal has its own programmable gain amplifier (PGA) for volume
adjustment and can be routed directly to the playback path output
mixers, bypassing the ADCs. An automatic level control (ALC)
can also be implemented to keep the recording volume constant.
2
S, left-
Rev. C | Page 23 of 80
The ADCs and DACs are high quality, 24-bit Σ-Δ converters
that operate at selectable 64× or 128× oversampling ratios. The
base sampling rate of the converters is set by the input clock rate
and can be further scaled with the converter control register
settings. The converters can operate at sampling frequencies
from 8 kHz to 96 kHz. The ADCs and DACs also include very
fine-step digital volume controls.
The playback path allows input signals and DAC outputs to be
mixed into various output configurations. Headphone drivers
are available for a stereo headphone output, and the other output
pins are capable of differentially driving an earpiece speaker.
Capless headphone outputs are possible with the use of the
mono output as a virtual ground connection. The stereo line
outputs can be used as either single-ended or differential
outputs and as an optional mix-down mono output.
The ADAU1361 can generate its internal clocks from a wide
range of input clocks by using the on-board fractional PLL.
The PLL accepts inputs from 8 MHz to 27 MHz.
The ADAU1361 is provided in a small, 32-lead, 5 mm × 5 mm
LFCSP with an exposed bottom pad.
ADAU1361