ADAU1361BCPZ Analog Devices Inc, ADAU1361BCPZ Datasheet - Page 38

• Manufacturer Part Number: ADAU1361BCPZ
• Description: IC CODEC 24B PLL 32LFCSP
• Manufacturer: Analog Devices Inc
• Type: Audio Codecr

Specifications of ADAU1361BCPZ

• Data Interface: Serial
• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• Voltage - Supply, Analog: 1.8 V ~ 3.6 V
• Voltage - Supply, Digital: 1.8 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-VFQFN, CSP Exposed Pad
• Audio Codec Type: Stereo
• No. Of Adcs: 2
• No. Of Dacs: 2
• No. Of Input Channels: 6
• No. Of Output Channels: 7
• Adc / Dac Resolution: 24bit
• Adcs / Dacs Signal To Noise Ratio: 101dB
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADAU1361
CONTROL PORTS
The ADAU1361 can operate in one of two control modes:
•
•
The ADAU1361 has both a 4-wire SPI control port and a
2-wire I
registers. The part defaults to I
SPI control mode by pulling the CLATCH pin low three times.
The control port is capable of full read/write operation for all
addressable registers. The ADAU1361 must have a valid master
clock in order to write to all registers except for Register R0
(Address 0x4000) and Register R1 (Address 0x4002).
All addresses can be accessed in both a single-address mode
or a burst mode. The first byte (Byte 0) of a control port write
contains the 7-bit chip address plus the R/ W bit. The next two
bytes (Byte 1 and Byte 2) together form the subaddress of the
register location within the ADAU1361. This subaddress must
be two bytes long because the memory locations within the
ADAU1361 are directly addressable and their sizes exceed the
range of single-byte addressing. All subsequent bytes (starting
with Byte 3) contain the data. The number of bytes per word
depends on the type of data that is being written.
The control port pins are multifunctional, depending on the
mode in which the part is operating. Table 20 describes these
multiple functions.
Table 20. Control Port Pin Functions
Pin Name
SCL/CCLK
SDA/COUT
ADDR1/CDATA
ADDR0/CLATCH
BURST MODE WRITING AND READING
Burst mode addressing, where the subaddresses are automatically
incremented at word boundaries, can be used for writing large
amounts of data to contiguous registers. This increment happens
automatically after a single-word write or read unless a stop condi-
tion is encountered (I
burst write starts like a single-word write, but following the first
data-word, the data-word for the next immediate address can be
written immediately without sending its two-byte address.
The registers in the ADAU1361 are one byte wide with the
exception of the PLL control register, which is six bytes wide.
The autoincrement feature knows the word length at each
subaddress, so the subaddress does not need to be specified
manually for each address in a burst write.
I
SPI control
2
C control
2
C bus control port. Both ports can be used to set the
I
SCL: input clock
SDA: open-collector
input/output
I
I
2
2
2
C Address Bit 1: input
C Address Bit 0: input
C Mode
2
C) or CLATCH is brought high (SPI). A
2
C mode, but it can be put into
SPI Mode
CCLK: input clock
COUT: output
CDATA: input
CLATCH: input
Rev. C | Page 38 of 80
The subaddresses are autoincremented by 1 following each
read or write of a data-word, regardless of whether there is a
valid register word at that address. Address holes in the register
map can be written to or read from without consequence. In
the ADAU1361, these address holes exist at Address 0x4001,
Address 0x4003 to Address 0x4007, Address 0x402E, and
Address 0x4032 to Address 0x4035. A single-byte write to these
registers is ignored by the ADAU1361, and a read returns a
single byte 0x00.
I
The ADAU1361 supports a 2-wire serial (I
microprocessor bus driving multiple peripherals. Two pins,
serial data (SDA) and serial clock (SCL), carry information
between the ADAU1361 and the system I
In I
meaning that it cannot initiate a data transfer. Each slave device
is recognized by a unique address. The address and R/ W byte
format is shown in
seven bits of the I
ADAU1361 are set by the levels on the ADDR1 and ADDR0
pins. The LSB of the address—the R/
read or write operation. Logic Level 1 corresponds to a read
operation, and Logic Level 0 corresponds to a write operation.
Table 21. ADAU1361 I
Bit 0
0
The SDA and SCL pins should each have a 2 kΩ pull-up resistor
on the line connected to it. The voltage on these signal lines
should not be higher than IOVDD (1.8 V to 3.3 V).
Addressing
Initially, each device on the I
monitors the SDA and SCL lines for a start condition and
the proper address. The I
establishing a start condition, defined by a high-to-low transition
on SDA while SCL remains high. This indicates that an address/
data stream follows. All devices on the bus respond to the start
condition and shift the next eight bits (the 7-bit address plus the
R/ W bit) MSB first. The device that recognizes the transmitted
address responds by pulling the data line low during the ninth
clock pulse. This ninth bit is known as an acknowledge bit. All
other devices withdraw from the bus at this point and return to
the idle condition.
2
C PORT
2
C mode, the ADAU1361 is always a slave on the bus,
Bit 1
1
Bit 2
1
2
C write. Bits[5:6] of the I
Table 21
2
Bit 3
1
C Address and Read/ Write Byte Format
2
C master initiates a data transfer by
. The address resides in the first
2
C bus is in an idle state and
Bit 4
0
W bit—specifies either a
Bit 5
ADDR1
2
C master controller.
2
2
C-compatible)
C address for the
Bit 6
ADDR0
Bit 7
R/W