DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 15

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

3. DS21FF44 (4 X 4) PCB LAND PATTERNS
The diagram shown below is the pin pattern that is placed on the target PCB. This is the same pattern that
would be seen as viewed through the MCM from the top.
Figure 3-1. PIN PATTERN FOR TARGET PCB (4 X 4)
W
G
M
A
B
C
D
E
H
K
N
P
R
U
V
Y
F
J
L
T
rsync
rsync
tneg
tneg
sync
rpos
rpos
rpos
tpos
rser
tclk
tser
tsig
rclk
rser
tclk
tser
rclk
1
rch
blk
rch
blk
ts
1
1
1
1
2
2
2
2
2
2
5
5
5
5
5
6
6
6
6
6
tsync
rsync
dvdd
sync
dvdd
rneg
rneg
tpos
tpos
rneg
tneg
rpos
rclk
sys
rsig
tclk
rsig
sys
tsig
2
rch
blk
clk
clk
ts
1
1
1
1
2
2
2
2
2
8
5
5
5
2
5
6
6
6
6
6
sync1
rsync
tsync
dvdd
tpos
tneg
rneg
tpos
dvss
rneg
rsig
tser
rser
rclk
tsig
rclk
tser
rch
blk
sys
tclk
3
clk
ts
1
1
1
1
3
2
2
8
2
5
5
5
8
8
8
2
6
8
6
rsync
tsync
dvdd
tsync
rpos
dvss
sync
rpos
sync
dvss
cs2*
tser
tsig
rsig
tsig
rser
rsig
rser
sys
sys
4
clk
clk
ts
ts
4
1
1
3
1
2
3
3
8
2
5
5
8
8
8
9
3
6
6
tsync
tsync
rsync
tsync
dvss
tneg
sync
tpos
tneg
rpos
rsig
tser
tclk
sys
tclk
sys
tclk
rch
tsig
sys
5
clk
clk
blk
clk
ts
4
1
3
1
3
3
3
2
3
8
5
8
8
8
8
7
7
7
6
7
rsync
dvss
clksi
rser
rsig
tser
rch
tclk
rch
rclk
6
blk
blk
1
3
3
3
7
7
7
7
7
rsync
tsync
mclk
dvdd
dvdd
sync
rneg
tpos
tser
rser
7
ts
4
8
1
4
3
7
2
7
7
7
rch
blk
rser4
rsig4
sync
dvss
sync
cs1*
tneg
sys
8
clk
rch
blk
10
ts
ts
4
4
4
2
7
9
rneg
rpos
rneg
dvss
rneg
rclk
rclk
tsig
tser
sys
9
clk
10
10
4
4
4
3
1
9
9
7
15 of 117
10
tneg
tpos
rpos
tpos
tsig
rclk
rsig
tsig
rclk
jtdi
10
10
10
4
4
4
3
9
9
11
dvdd
rsync
dvss
tneg
rpos
rneg
rser
rsig
tclk
tsig
16
13
13
10
10
10
4
4
9
9
12
rsync
tsync
tpos
dvdd
tneg
rser
rser
rclk
sys
rch
16
16
16
16
13
clk
11
10
blk
10
10
3
13
tsync
rsync
tsync
rneg
sync
test
tser
sys
tclk
tclk
clk
16
13
13
13
10
10
10
ts
9
9
14
rpos
tpos
rneg
tpos
tneg
jtclk
sys
rclk
clk
fs1
fs0
16
16
16
13
13
9
9
15
rsync
tsync
tneg
rpos
sync
cs3*
rsig
rsig
tsig
bts
16
16
15
13
13
11
ts
9
9
16
dvdd
tsync
dvdd
tsync
tsync
jtms
dvss
tsig
rser
rser
tser
rser
rser
tser
rch
rch
int*
tclk
tclk
wr*
16
blk
16
15
blk
13
13
13
13
12
12
12
11
11
11
4
3
9
3
17
rsync
rsync
sync
dvdd
jtrst*
mux
jtdot
rneg
sync
rsig
tser
tclk
rclk
sys
rch
rch
16
15
15
15
14
A6
A7
13
D6
D7
12
clk
12
blk
12
blk
11
11
11
ts
ts
4
18
tsync
rsync
rpos
tneg
tpos
tneg
tser
tser
rch
rclk
sys
tsig
tclk
tsig
rclk
16
blk
15
15
15
rd*
14
A4
A5
14
14
D4
D5
clk
14
12
12
11
11
11
11
11
tssync
19
rsync
dvss
dvdd
jtdof
tpos
tneg
cs4*
tpos
rpos
tneg
rpos
tclk
rsig
tsig
rsig
A2
A3
D2
D3
15
15
14
14
14
14
14
12
12
12
11
11
4
3
20
sync
dvss
sync
dvss
rpos
rneg
rneg
rneg
tpos
tsig
sys
rser
rclk
rsig
tser
clk
A0
A1
rch
blk
D0
D1
15
15
15
15
15
14
14
14
14
14
12
12
12
12
ts
ts
4
3