DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 84

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

21.
21.1. DESCRIPTION
The DS21Q44 IEEE 1149.1 design supports the standard instruction codes SAMPLE/PRELOAD,
BYPASS, and EXTEST. Optional public instructions included with this design are HIGHZ, CLAMP, and
IDCODE. See Figure 21-1 for a block diagram. The DS21Q44 contains the following items which meet
the requirements set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture.
The DS21FT42 should be considered as 3 individual DS21Q42 devices. The DS21FF44 should be
considered as 4 individual DS21Q44 devices.
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
The JTAG feature is only available when the DS21Q44 feature set is selected (FMS = 0). The JTAG
feature is disabled when the DS21Q44 is configured for emulation of the DS21Q43 (FMS = 1). FMS is
connected to ground for the DS21FF44/DS21FT44.
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins; JTRST*, JTCLK, JTMS, JTDI, and JTDO. See
the pin descriptions for details.
Figure 21-1. BOUNDARY SCAN ARCHITECTURE
JTAG-BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
10K
+V
JTDI
10K
+V
JTMS
Test Access Port
Boundary Scan
Identification
Instruction
Bypass
Register
Register
Controller
Register
Register
JTCLK
10K
+V
JTRST
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Select
Output Enable
MUX
JTDO