DS21FF44 Maxim Integrated Products, DS21FF44 Datasheet - Page 39

• Manufacturer Part Number: DS21FF44
• Description: IC FRAMER E1 4X4 16CH 300-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS21FF44

• Controller Type: E1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 300mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 300-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

constant Remote Alarm will be transmitted if the framer cannot find CRC4 multiframe synchronization
within 400ms as per G.706.
It is an illegal state to have both CCR2.4 and CCR2.5 set to one at the same time.
CCR3: COMMON CONTROL REGISTER 3 (Address = 1B Hex)
(MSB)
TESE
SYMBOL
TCBFS
TIRFS
RCLA
RSRE
THSE
TBCS
TESE
–
TCBFS
POSITION
CCR3.7
CCR3.6
CCR3.5
CCR3.4
CCR3.3
CCR3.2
CCR3.1
CCR3.0
TIRFS
Transmit Side Elastic Store Enable
0 = elastic store is bypassed
1 = elastic store is enabled
Transmit Channel Blocking Registers (TCBR) Function
Select
0 = TCBRs define the operation of the TCHBLK output pin
1 = TCBRs define which signaling bits are to be inserted
Transmit Idle Registers (TIR) Function Select. See Section
15 for details.
0 = TIRs define in which channels to insert idle code
1 = TIRs define in which channels to insert data from RSER
(i.e., Per Channel Loopback function)
Not Assigned. Should be set to zero when written.
Receive Side Signaling Reinsertion Enable. See Section 14
for details.
0 = do not reinsert signaling bits into the data stream presented
at the RSER pin
1 = reinsert the signaling bits into data stream presented at the
RSER pin
Transmit Side Hardware Signaling Insertion Enable. See
Section 14 for details.
0 = do not insert signaling from the TSIG pin into the data
stream presented at the TSER pin
1 = insert signaling from the TSIG pin into the data stream
presented at the TSER pin
Transmit Side Backplane Clock Select
0 = if TSYSCLK is 1.544MHz
1 = if TSYSCLK is 2.048MHz
Receive Carrier Loss (RCL) Alternate Criteria
0 = RCL declared upon 255 consecutive zeros (125µs)
1 = RCL declared upon 2048 consecutive zeros (1ms)
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RSRE
NAME AND DESCRIPTION
THSE
TBCS
RCLA
(LSB)