DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 16

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

Figure 7b demonstrates how a system designer would use
DP8419 Mode Descriptions
Once it is started a hidden refresh will continue even if
RFCK goes low However CS must be high throughout the
refresh (until RASIN goes high)
These hidden refreshes are valuable in that they do not
delay accesses When determining the duty cycle of RFCK
the high time should be maximized in order to maximize the
probability of hidden refreshes If a hidden refresh doesn’t
happen then a refresh request will occur on RFI O when
RFCK goes low After receiving the request the system
must perform a refresh while RFCK is low This may be
done by going to mode 1 and allowing an automatic refresh
(see mode 1 description) This refresh must be completed
while RFCK is low thus the RFCK low time is determined by
the worst-case time required by the system to respond to a
refresh request
(c) Mode 5 Refresh (Hidden Refresh) with mode 0 Refresh
This refresh scheme is identical to that in (b) except that
after receiving a refresh request mode 0 is entered to do
the refresh (see mode 0 description) The refresh request is
terminated (RFI O goes high) as soon as mode 0 is en-
tered This method requires more control than using mode 1
(auto-refresh) however it may be desirable if the mode 1
refresh time is considered to be excessive
Example
the DP8419 in mode 5 based on certain characteristics of
his system
(External Refresh)
FIGURE 7a Hidden Refreshing (Mode 5) and Forced Refreshing (Mode 1) Timing
(Continued)
16
Figure 7c illustrates a similar example using the DP8418 to
System Characteristics
Using the DP8419 (see Figure 7b )
drive two 32-bit banks
1) DRAM used has min t
2) DRAM address is valid from time T
3) four banks of twenty-two 256K memory chips each are
1) Tie pin 4 (RAHS) high to guarantee a 15 ns minimum
2) Generate RASIN no earlier than time T
3) Tie ADS high since latching the DRAM address on the
4) Connect the first 18 system address bits to R0-R8 and
5) Connect each RAS output of the DP8419 to the RAS
min t
memory cycle
being driven
t
switching characteristics) so that the row address is
valid on the DRAM address inputs before RAS occurs
DP8419 is not necessary
C0-C8 and bits 19 and 20 to B0 and B1
inputs of the DRAMs of one bank of the memory array
connect Q0-Q8 of the DP8419 to A0-A8 of all DRAMs
connect CAS of the DP8419 to CAS of all the DRAMs
RAH
ASR
which is sufficient for the DRAMs being used
of 0 ns
RAH
requirement of 15 ns and
V
to the end of the
V
a
TL F 8396– 18
t
ASRL
(see