DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 7

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

Pin Definitions
indicating that no hidden refresh was performed while RFCK
was high When this pin is set low by an external gate the
on-chip refresh counter is reset to all zeroes
WIN Write Enable Input
WE Write Enable Output - WE follows WIN unconditional-
ly
RAHS Row Address Hold Time Select - Selects the t
to be generated by the DP8419 delay line to allow use with
fast or slow DRAMs
CAS Column Address Strobe Output - In mode 5 and in
mode 4 with CASIN low before R C goes low CAS goes
low automatically after the column address is valid on the
address outputs In mode 4 CAS follows CASIN directly af-
ter R C goes low allowing for nibble accessing CAS is al-
ways high during refresh
RAS 0 –3 Row Address Strobe Outputs - The enabled
RAS output (see Table II) follows RASIN directly during an
access During refresh all RAS outputs are enabled
B0 B1 Bank Select Inputs - These pins are decoded to
enable one of the four RAS outputs during an access (see
Table I and Table II)
Conditions for All Modes
INPUT ADDRESSING
The address block consists of a row-address latch a col-
umn-address latch and a resettable refresh counter The
address latches are fall-through when ADS is high and latch
when ADS goes low If the address bus contains valid ad-
dresses until after CAS goes low at the end of the memory
cycle ADS can be permanently high Otherwise ADS must
go low while the addresses are still valid
DRIVE CAPABILITY
The DP8419 has timing parameters that are specified driv-
ing the typical capacitance (including traces) of 88 5V-only
DRAMs Since there are 4 RAS outputs each is specified
driving one-fourth of the total memory CAS WE and the
address outputs are specified driving all 88 DRAMs
The graph in Figure 10 may be used to determine the slight
variations in timing parameters due to loading conditions
other than 88 DRAMs
(Strobed by ADS)
B1
B1
(Strobed by ADS)
0
1
0
0
1
1
TABLE II DP8418 Memory Bank Decode
Bank Select
Bank Select
TABLE I DP8417 DP8419 DP8419X
Memory Bank Decode
NC
B0
X
X
0
1
0
1
(Continued)
RAS
RAS
Enabled RAS
Enabled RAS
0
2
RAS
RAS
RAS
RAS
and RAS
and RAS
0
1
2
3
n
n
1
3
RAH
7
ure 1a )
Because of distributed trace capacitance and inductance
and DRAM input capacitance current spikes can be creat-
ed causing overshoots and undershoots at the DRAM in-
puts that can change the contents of the DRAMs or even
destroy them To reduce these spikes a damping resistor
(low inductance carbon) should be inserted between the
DP8419 outputs and the DRAMs as close as possible to
the DP8419 The damping resistor values may differ de-
pending on how heavily an output is loaded These resistors
should be determined by the first prototypes (not wire-
wrapped due to the larger distributed capacitance and in-
ductance) Resistors should be chosen such that the tran-
sition on the control outputs is critically damped Typical
values will be from 15
ing used with the larger memory arrays Note that AC pa-
rameters are specified with 15
more information see AN-305 ‘‘Precautions to Take When
Driving Memories’’
DP8419 DRIVING ANY 16k 64k or 256k DRAMs
The DP8419 can drive any 16k 64k or 256k DRAMs All 16k
DRAMs use basically the same configuration including the
5V-only version Hence in most applications different man-
ufacturers’ DRAMs are interchangeable (for the same sup-
ply-rail chips) and the DP8419 can drive them all (see Fig-
There are three basic configurations for the 5V-only 64k
DRAMs a 128-row by 512-column array with an on-RAM
refresh counter a 128-row by 512-column array with no on-
RAM refresh counter and a 256-row by 256-column array
with no on-RAM refresh counter The DP8419 can drive all
three configurations and allows them all to be interchange-
able (as shown in Figures 1b and 1c ) providing maximum
flexibility in the choice of DRAMs Since the 9-bit on-chip
refresh counter can be used as a 7-bit refresh counter for
the 128-row configuration or as an 8-bit refresh counter for
the 256-row configuration the on-RAM refresh counter if
present is never used
256k DRAMs require all 18 of the DP8419’s address inputs
to select one memory location within the DRAM RAS-only
refreshing with the nine-bit refresh-counter on the DP8419
makes CAS before RAS refreshing available on 256k
DRAMs unnecessary
READ WRITE AND READ-MODIFY-WRITE CYCLES
The output signal WE determines what type of memory
access cycle the memory will perform If WE is kept high
while CAS goes low a read cycle occurs If WE goes low
before CAS goes low a write cycle occurs and data at DI
(DRAM input data) is written into the DRAM as CAS goes
low If WE goes low later than t
a read occurs and DO (DRAM output data) becomes valid
then data DI is written into the same address in the DRAM
as WE goes low In this read-modify-write case DI and DO
cannot be linked together WE always follows WIN directly
to determine the type of access to be performed
POWER-UP INITIALIZE
When V
clears the refresh counter and the internal control flip-flops
CC
is first applied to the DP8419 an initialize pulse
to 100
CWD
with the lower values be-
after CAS goes low first
damping resistors For