DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 8

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

Figure 2 shows the Externally Controlled Refresh timing In
Mode Features Summary
Y
Y
Y
Y
Y
Y
Y
DP8419 Mode Descriptions
MODE 0 –EXTERNALLY CONTROLLED REFRESH
this mode the refresh counter contents are multiplexed to
the address outputs All RAS outputs are enabled to follow
RASIN so that the row address indicated by the refresh
counter is refreshed in all DRAM banks when RASIN goes
low The refresh counter increments when RASIN goes
high RFSH should be held low at least until RASIN goes
high (they may go high simultaneously) so that the refresh
address remains valid and all RAS outputs remain enabled
throughout the refresh
4 modes of operation 2 access and 2 refresh
Automatic or external control selected by the user
Auto access mode provides RAS
change and then CAS automatically
Choice between two different values of t
cess mode
CAS controlled independently in external control mode
allowing for nibble mode accessing
Automatic refreshing can make refreshes transparent to
the system
CAS is inhibited during refresh cycles
row to column
RAH
in auto-ac-
8
A burst refresh may be performed by holding RFSH low and
toggling RASIN until all rows are refreshed It may be useful
in this case to reset the refresh counter just prior to begin-
ning the refresh The refresh counter resets to all zeroes
when RFI O is pulled low by an external gate The refresh
counter always counts to 511 before rolling over to zero If
there are 128 or 256 rows being refreshed then Q7 or Q8
respectively going high may be used as an end-of-burst
indicator
In order that the refresh address is valid on the address
outputs prior to the RAS lines going low RFSH must go low
before RASIN The setup time required is given by t
the Switching Characteristics This parameter may be ad-
justed using Figure 10 for loading conditions other than
those specified
Mode
0
1
4
5
TABLE III DP8419 Mode Select Options
(RFSH) M2
0
0
1
1
M0
0
1
0
1
Externally Controlled Refresh
Auto Refresh– Forced
Externally Controlled Access
Auto Access (Hidden Refresh)
Mode of Operation
RFLRL
in