DP8419N-70 National Semiconductor, DP8419N-70 Datasheet - Page 18

• Manufacturer Part Number: DP8419N-70
• Description: IC CTRLR 256K DRAM 48-DIP
• Manufacturer: National Semiconductor

Specifications of DP8419N-70

• Controller Type: Dynamic RAM (DRAM) Controller, Drivers
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 150mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 48-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP8419N-70

Applications
If one desires a memory interface containing the DP8419
that minimizes the number of external components required
modes 5 and 1 should be used These two modes provide
1) Automatic access to memory (in mode 5 only one signal
2) Hidden refresh capability (refreshes are performed auto-
3) Refresh request capability (if no hidden refresh took
4) Automatic forced refresh (If a refresh request is generat-
Some items to be considered when integrating the DP8419
into a system design are
1) The system designer should ensure that a DRAM access
2) One should always guarantee that the DP8419 is enabled
3) One should bring RASIN low even during non-local ac-
4) At lower frequencies (under 10 Mhz) it becomes increas-
5) Many times it is possible to only add WAIT states during
The DP84XX2 family of inexpensive preprogrammed medi-
um Programmable Array Logic devices (PALs) have been
developed to provide an easy interface between various
RASIN is required in order to access memory)
matically while in mode 5 when non-local accesses are
taking place as determined by CS)
place while RFCK was high a refresh request is generat-
ed at the RFI O pin when RFCK goes high)
ed while in mode 5 as described above external logic
should switch the DP8419 into mode 1 to do an automat-
ic forced refresh No other external control signals need
be issued WAIT states can be inserted into the proces-
sor machine cycles if the system tries to access memory
while the DP8419 is in mode 1 doing a forced refresh)
not be in progress when a refresh mode is entered Simi-
larly one should not attempt to start an access while a
refresh is in progress The parameter t
the minimum time from RFSH high to RASIN going low to
initiate an access
for access prior to initiating the access (see t
cess cycles when in mode 5 in order to maximize the
chance of a hidden refresh occurring
ingly important to differentiate between READ and
WRITE cycles RASIN generation during READ cycles
can take place as soon as one knows that a processor
READ access cycle has started WRITE cycles on the
other hand cannot start until one knows that the data to
be written at the DRAM inputs will be valid a setup time
before CAS (column address strobe) goes true at the
DRAM inputs Therefore in general READ cycles can be
initiated earlier than WRITE cycles
READ cycles and have no WAIT states during WRITE
cycles This is because it generally takes less time to
write data into memory than to read data from memory
RFHRL
CSRL1
specifies
)
18
Figure 8 shows a general block diagram for a system using
microprocessors and the DP84XX family of DRAM control-
ler drivers These PALs interface to all the necessary con-
trol signals of the particular processor and the DP8419 The
PAL controls the operation of the DP8419 in modes 5 and 1
while meeting all the critical timing considerations discussed
above The refresh clock RFCK may be divided down from
the processor clock using an IC counter such as the
DM74LS393 or the DP84300 programmable refresh timer
The DP84300 can provide RFCK periods ranging from
15 4 s to 15 6 s based on an input clock of 2 to 10 MHz
the DP8419 in modes 1 and 5 Figure 9 shows possible
timing diagrams for such a system (using WAIT to prohibit
access when refreshing) Although the DP84XX2 PALs are
offered as standard peripheral devices for the DP84XX
DRAM controller drivers the programming equations for
these devices are provided so the user may make minor
modification for unique system requirements
ADVANTAGES OF DP8419 OVER
A DISCRETE DYNAMIC RAM CONTROLLER
1) The DP8419 system solution takes up much less board
2) Less effort is needed to design a memory system The
3) Less skew in memory timing parameters because all crit-
4) Our switching characteristics give the designer the critical
space because everything is on one chip (latches re-
fresh counter control logic multiplexers drivers and in-
ternal delay lines)
DP8419 has automatic modes (1 and 5) which require a
minimum of external control logic Also programmable ar-
ray logic devices (PALs) have been designed which allow
an easy interface to most popular microprocessors (Mo-
torola 68000 family National Semiconductor 32032 fami-
ly Intel 8086 family and the Zilog Z8000 family)
ical components are on one chip (many discrete drivers
specify a minimum on-chip skew under worst-case condi-
tions but this cannot be used if more then one driver is
needed such as would be the case in driving a large
dynamic RAM array)
timing specifications based on TTL output levels (low
0 8V high
timing parameters are specified on the DP8419
A) driving 88 DRAM’s over a temperature range of 0– 70
B) under worst-case driving conditions with all outputs
degrees centigrade (no extra drivers are needed)
switching simultaneously (most discrete drivers on the
market specify worst-case conditions with only one
output switching at a time this is not a true worst-case
condition )
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2 4V) at a specified load capacitance All
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