CS8952-CQZ Cirrus Logic Inc, CS8952-CQZ Datasheet - Page 26

• Manufacturer Part Number: CS8952-CQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-CQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Supply Voltage Range: 4.75V To 5.25V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1206

STATUS Pins
SERIAL MANAGEMENT Pins
RECEIVE DATA Pins
TRANSMIT DATA Pins
The interface uses TTL signal levels, which are
compatible with devices operating at a nominal
supply voltage of either 5.0 or 3.3 volts. It is capa-
ble of supporting either 10 Mb/s or 100 Mb/s data
rates transparently. That is, all signaling remains
identical at either data rate; only the nominal clock
frequency is changed.
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
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COL - Collision indication, valid only for
half duplex modes.
CRS - Carrier Sense indication
MDIO - a bi-directional serial data path
MDC - clock for MDIO (16.7 MHz max)
MII_IRQ - Interrupt indicating change in
the Interrupt Status Register (address 11h)
RXD[3:0] - Parallel data output path
RX_CLK - Recovered clock output
RX_DV - Indicates when receive data is
present and valid
RX_ER - Indicates presence of error in re-
ceived data
RX_EN - Can be used to tri-state receiver
output pins
TXD[3:0] - Parallel data input path
TX_CLK - Transmit clock
TX_EN - Indicates when transmit data is
present and valid
TX_ER - Request to transmit a 100BASE-
T HALT symbol, ignored for 10BASE-T
operation.
4.1
Data frames transmitted through the MII have the
following format:
Each frame is preceded by an inter-frame gap. The
inter-frame gap is an unspecified time during
which no data activity occurs on the media as indi-
cated by the de-assertion of CRS for the receive
path and TX_EN for the transmit path.
The Preamble consists of seven bytes of 10101010.
The Start of Frame Delimiter consists of a single
byte of 10101011.
Data may be any number of bytes.
The End of Frame Delimiter is conveyed by the de-
assertion of RX_DV and TX_EN for receive and
transmit paths, respectively.
Transmission and/or reception of each byte of data
is done one nibble at a time in the following order:
4.2
The presence of recovered data on the RXD[3:0]
bus is indicated by the assertion of RX_DV.
RX_DV will remain asserted from the beginning of
the preamble (or Start of Frame Delimiter if pream-
ble is not used) to the End of Frame Delimiter.
Once RX_DV is asserted, valid data will be driven
Preamble
(7 Bytes)
MII
Nibble
Stream
First Bit
MSB
LSB
MII Frame Structure
MII Receive Data
First
Nibble
LSB
D0
D1
D2
D3
Delimiter
(1 Byte)
Start of
Frame
D0
D1 D2 D3 D4 D5 D6 D7
MAC’s Serial Bit Stream
Data
CS8952
Delimiter
Second
Nibble
MSB
End of
Frame
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