CS8952-CQZ Cirrus Logic Inc, CS8952-CQZ Datasheet - Page 55

• Manufacturer Part Number: CS8952-CQZ
• Description: IC TXRX 100/10 PHY 100TQFP
• Manufacturer: Cirrus Logic Inc
• Type: Transceiverr

Specifications of CS8952-CQZ

• Package / Case: 100-TQFP, 100-VQFP
• Protocol: MII
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Transceivers
• Number Of Transceivers: 1
• Standard Supported: 100BASE-FX or 100BASE-TX or 10BASE-T
• Data Rate: 10 Mbps or 100 Mbps
• Supply Voltage (max): 6 V
• Supply Voltage (min): - 0.3 V
• Supply Current (max): +/- 10 mA
• Maximum Operating Temperature: + 70 C
• Supply Voltage Range: 4.75V To 5.25V
• Logic Case Style: TQFP
• No. Of Pins: 100
• Operating Temperature Range: 0°C To +70°C
• Msl: MSL 3 - 168 Hours
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Driver Case Style: TQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1206

6.17
CrystalLAN™ 100BASE-X and 10BASE-T Transceiver
DS206F1
15
14
13
12
11
10
9
Strip Preamble
BIT
Bad SSD
Enable
15
7
Bad SSD Enable
Bypass 4B5B
Bypass Scrambler
Bypass Symbol
Alignment
ENDEC Loopback
FX Drive
Remote Loopback
Loopback, Bypass, and Receiver Error Mask Register - Address 18h
NAME
Alternate FDX
Bypass 4B5B
CRS
14
6
Read/Write 1
Read/Write Reset to the value
Read/Write Reset to the value
Read/Write Reset to the value
Read/Write 0
Read/Write 0
Read/Write 0
Scrambler
Loopback
TYPE
Transmit
Disable
Bypass
13
5
on the BP4B5B
pin.
on the BPSCR
pin.
on the BPALIGN
pin.
Report Select
Code Error
Alignment
Bypass
Symbol
RESET
12
4
Premature End
Error Report
Loopback
ENDEC
When set, this bit enables the reporting of a bad SSD
(False-Carrier event) on the MII. These events will be
reported by setting RX_ER=1, RX_DV=0, and
RXD[3:0]=1110.
If the 4B5B encoders are being bypassed, this event
will be reported by setting RX_DV=0 and
RXD[4:0]=11110. If symbol alignment is bypassed,
the CS8952 does not detect carrier, and thus will not
report bad SSD events.
When set, this bit causes the receive 5B4B decoder
and the transmit 4B5B encoder to be bypassed.
When set, this bit causes the receive descrambler
and the transmit scrambler blocks to be bypassed,
and the CS8952 accepts NRZI data from an external
100BASE-FX optical module through pins RX_NRZ+
and RX_NRZ-.
When set, this bit causes the following functions to
be bypassed: receiver descrambling, symbol align-
ment and decoding, transmit symbol encoding, and
transmit scrambling.
When set, the 10BASE-T internal Manchester
encoder output is connected to the decoder input.
When clear, the CS8952 is configured for normal
operation.
This bit controls the drive strength of the 100BASE-
FX PECL interface drivers. When clear, the drivers
are optimized for a 50 Ω load. When set, the drivers
are optimized for a 150 Ω load.
When set, data received from the link is looped back
at the MII and sent back out to the link. Received
data will be presented on the MII pins. Transmit data
at the MII will be ignored.
Note: Setting Remote Loopback and PMD Loopback
simultaneously will cause neither loopback mode to
be entered, and should not be done.
Select
11
3
Report Enable
Link Error
FX Drive
10
2
DESCRIPTION
Report Enable
Packet Error
Loopback
Remote
9
1
Report Enable
CS8952
Code Error
Loopback
PMD
8
0
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