DS26521LN+ Maxim Integrated Products, DS26521LN+ Datasheet - Page 10

• Manufacturer Part Number: DS26521LN+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521LN+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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2.5
FEATURE HIGHLIGHTS
General
Single-port member of the TEX-series transceiver family of devices
Software compatible with the DS26522 dual, DS26524 quad, and DS26528 octal transceivers
64-pin LQFP package
3.3V supply with 5V tolerant inputs and outputs
IEEE 1149.1 JTAG boundary scan
Development support includes evaluation kit, driver source code, and reference designs
Line Interface
Requires a single master clock (MCLK) for both E1 and T1 operation. Master clock can be 1.544MHz,
2.048MHz, 3.088MHz, 4.096MHz, 6.276MHz, 8.192MHz, 12.552MHz, or 16.384MHz
Fully software configurable
Short- and long-haul applications
Ranges include 0dB to -43dB, 0dB to -30dB, 0dB to 20dB, and 0dB to -12dB for E1; 0dB to -36dB, 0dB to
30dB, 0dB to 20dB, and 0dB to -15dB for T1
Receiver signal level indication from -2.5dB to -36dB in T1 mode and -2.5dB to -44dB in E1 mode in 2.5dB
increments
Internal receive termination option for 75Ω, 100Ω, 110Ω, and 120Ω lines
Monitor application gain settings of 14dB, 20dB, 26dB, and 32dB
G.703 receive synchronization signal mode
Flexible transmit waveform generation
T1 DSX-1 line build-outs
T1 CSU line build-outs of 0dB, -7.5dB, -15dB, and -22.5dB
E1 waveforms include G.703 waveshapes for both 75Ω coax and 120Ω twisted cables
Analog loss-of-signal detection
AIS generation independent of loopbacks
Alternating ones and zeros generation
Receiver power-down
Transmitter power-down
Transmitter short-circuit limiter with current-limit-exceeded indication
Transmit open-circuit-detected indication
Clock Synthesizer
Output frequencies include 2.048MHz, 4.096MHz, 8.192MHz, and 16.384MHz
Derived from user-selected recovered receive clock
Jitter Attenuator
32-bit or 128-bit crystal-less jitter attenuator
Requires only a 1.544MHz or 2.048MHz master clock or multiple thereof, for both E1 and T1 operation
Can be placed in either the receive or transmit path or disabled
Limit trip indication
Framer/Formatter
Fully independent transmit and receive functionality
Full receive and transmit path transparency
T1 framing formats D4 and ESF per T1.403, and expanded SLC-96 support (TR-TSY-008)
E1 FAS framing and CRC-4 multiframe per G.704, G.706, and G.732 CAS multiframe
Transmit-side synchronizer
Transmit midpath CRC recalculate (E1)
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DS26521 Single T1/E1/J1 Transceiver