DS26521LN+ Maxim Integrated Products, DS26521LN+ Datasheet - Page 30

• Manufacturer Part Number: DS26521LN+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521LN+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4
8.4.1 Example Device Initialization Sequence
STEP 1: Reset the device by pulling the RESETB pin low, applying power to the device, or by using the software
reset bits outlined in Section 8.3. Clear all reset bits. Allow time for the reset recovery.
STEP 2: Check the device ID in the Device Identification register (IDR).
STEP 3: Write the
this write with at least a 300ns delay to allow the clock system to properly adjust.
STEP 4: Write the entire remainder of the register space with 00h, including reserved register locations.
STEP 5: Choose T1/J1 or E1 operation for the framers by configuring the T1/E1 bit in the
registers for each framer. Set the FRM_EN bit to 1 in the
signaling in E1 mode, program the
Control registers (TCR1:TCR4). Configure the Framer Receive Control registers
T1RCR2/E1RCR2, RCR3). Configure other framer features as appropriate.
STEP 6: Choose T1/J1 or E1 operation for the LIUs by configuring the T1J1E1S bit in the
Configure the line build-out for each LIU. Configure other LIU features as appropriate. Set the TE bit to turn on the
TTIP and TRING outputs.
STEP 7: Configure the elastic stores, HDLC controller, and BERT as needed.
STEP 8: Set the INIT_DONE bit in the
8.5
A set of global registers are located at 0F0h–0FFh and include global resets, global interrupt status, interrupt
masking, clock configuration, and the device ID registers. See the global register definitions in
common JTAG controller is used.
8.6
The port has a framer, LIU, BERT, jitter attenuator, and transmit/receive HDLC controller.
8.7
Figure 8-10
information registers and mask bits to the interrupt pin. When an interrupt occurs, the host can read the global
interrupt information registers GFISR, GLISR, and
host can then read the specific block’s interrupt information registers (TIIR, RIIR) and the latched status registers
(LLSR, BLSR) to further identify the source of the interrupt(s). If
the transmit-latched status or the receive-latched status registers for the source of the interrupt. All interrupt
information register bits are real-time bits that clear once the appropriate interrupt has been serviced and cleared,
as long as no additional, unmasked interrupt condition is present in the associated status register. The host must
clear all latched status bits by writing a 1 to the bit location of the interrupt condition that has been serviced.
Latched status bits that have been masked by the interrupt mask registers are masked from the interrupt
information registers. The interrupt mask register bits prevent individual latched status conditions from generating
an interrupt, but they do not prevent the latched status bits from being set. Therefore, when servicing interrupts, the
user should XOR the latched status with the associated interrupt mask in order to exclude bits for which the user
wished to prevent interrupt service. This architecture allows the application host to periodically poll the latched
status bits for noninterrupt conditions, while using only one set of registers.
Initialization and Configuration
Global Resources
Port Resources
Device Interrupts
diagrams the flow of interrupt conditions from their source status bits through the multiple levels of
GTCCR
register to correctly configure the system clocks. If supplying a 1.544MHz MCLK, follow
E1TAF
TMMR
and
and
RMMR
E1TNAF
GBISR
30 of 258
registers for each framer.
TMMR
to identify which block is causing the interrupt(s). The
registers as required. Configure the framer Transmit
TIIR
and
or
RMMR
RIIR
DS26521 Single T1/E1/J1 Transceiver
is the source, the host will then read
registers. If using software transmit
(RCR1 (T1)/RCR1
TMMR
LTRCR
Table
and
register.
RMMR
9-2. A
(E1),