DS26521LN+ Maxim Integrated Products, DS26521LN+ Datasheet - Page 22

• Manufacturer Part Number: DS26521LN+
• Description: IC TXRX T1/E1/J1 64-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26521LN+

• Number Of Drivers/receivers: 1/1
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI_SWAP
SPI_CPOL
SPI_CPHA
RCHBLK/
BPCLK
NAME
D[7]/
D[6]/
D[5]/
CLK
D[4]
D[3]
A12
A8
A7
A6
A5
A4
A3
A2
A1
A0
PIN
49
48
14
15
16
17
18
19
20
23
24
25
26
27
28
29
30
TYPE
O
O
I
I
I
I
I
I
Receive Channel Block/Receive Channel Block Clock. This pin can be
configured to output either RCHBLK or RCHCLK. RCHBLK is a user-
programmable output that can be forced high or low during any of the 24 T1 or 32
E1 channels. It is synchronous with RCLK when the receive-side elastic store is
disabled. It is synchronous with RSYSCLK when the receive-side elastic store is
enabled. This pin is useful for blocking clocks to a serial UART or LAPD controller
in applications where not all channels are used such as fractional service, 384kbps
service, 768kbps, or ISDN-PRI. Also useful for locating individual channels in drop-
and-insert applications, for external per-channel loopback, and for per-channel
conditioning.
RCHCLK. RCHCLK is a 192kHz (T1) or 256kHz (E1) clock that pulses high during
the LSB of each channel. It is synchronous with RCLK when the receive-side
elastic store is disabled. It is synchronous with RSYSCLK when the receive-side
elastic store is enabled. It is useful for parallel-to-serial conversion of channel data.
Backplane Clock. Programmable clock output that can be set to 2.048MHz,
4.096MHz, 8.192MHz, or 16.384MHz. The reference for this clock can be RCLK
from any of the LIU, 1.544MHz, or 2.048MHz frequency derived from MCLK or an
external reference clock. This allows for the IBO clock to reference from an
external source or the T1/J1/E1 recovered clock or the MCLK oscillator.
Address [12], [8:0]. This bus selects a specific register in the DS26521 during
read/write access. A12 is the MSB and A0 is the LSB. Note: A9, A10, and A11 are
internally pulled low. Connect device A12 to microprocessor A12 to ensure
software compatibility with other TEX-series transceivers. See Section
information.
Data [7]/SPI Interface Clock Polarity
D[7]: Bit 7 of the 16-bit or 8-bit data bus used to input data during register writes
and data outputs during register reads. Not driven when CS = 1.
SPI_CPOL: This signal selects the clock polarity when SPI_SEL = 1. See Section
8.1.3
Data [6]/SPI Interface Clock Phase
D[6]: Bit 6 of the 16-bit or 8-bit data bus used to input data during register writes,
and data outputs during register reads. Not driven when CS = 1.
SPI_CPHA: This signal selects the clock phase when SPI_SEL = 1. See Section
8.1.3
Data [5]/SPI Bit Order Swap
D[5]: Bit 5 of the 16-bit or 8-bit data bus used to input data during register writes,
and data outputs during register reads. Not driven when CSB = 1.
SPI_SWAP: This signal is active when SPI_SEL = 1. The address and data bit
order is swapped when SPI_SWAP is high. The R/W and B bit positions are never
changed in the control word.
0 = LSB is transmitted and received first.
1 = MSB is transmitted and received first.
Data [4]. Bit 4 of the 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when CSB = 1.
Data [3]. Bit 3 of the 8-bit data bus used to input data during register writes, and
data outputs during register reads. Not driven when CSB = 1.
MICROPROCESSOR INTERFACE
for detailed timing and functionality information. Default setting is low.
for detailed timing and functionality information. Default setting is low.
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FUNCTION
DS26521 Single T1/E1/J1 Transceiver
9
for further