ISP1302HN-T ST-Ericsson Inc, ISP1302HN-T Datasheet - Page 35

• Manufacturer Part Number: ISP1302HN-T
• Description: IC USB OTG TRANSCEIVER 24HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1302HN-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
ISP1302_1
Product data sheet
9.3.3.1 One-byte write
9.3.3.2 Multiple-byte write
9.3.3 Write format
Table 48.
A write operation can be performed as:
Table 49
Table 49.
Table 50
Table 50.
Bit
7 to 1
0
Byte
S
Device select
ACK
Register address K
ACK
Write data K
ACK
P
Byte
S
Device select
ACK
Register address K
ACK
Write data K
ACK
Write data K + 1
•
•
One-byte write to the specified register address.
Multiple-byte write to N consecutive registers, starting from the specified start
address. N defines the number of registers to write. If N = 1, only the start register is
written.
Symbol
A[6:0]
R/W
describes the transfer format for a one-byte write.
describes the transfer format for multiple-byte write.
I
Transfer format description for a one-byte write
Transfer format description for a multiple-byte write
2
C-bus slave address bit description
Description
Device Address: The device address of the ISP1302 is 01 0110 (A0), where
A0 is determined by pin ADR/PSW.
Read or write command.
0 — Write
1 — Read
Description
master starts with a START condition
master transmits the device address and write command bit R/W = 0
slave generates an acknowledgment
master transmits the address of register K
slave generates an acknowledgment
master writes data to register K
slave generates an acknowledgment
master generates a STOP condition
Description
master starts with a START condition
master transmits the device address and write command bit R/W = 0
slave generates an acknowledgment
master transmits the address of register K. This is the start address for
writing multiple data bytes to consecutive registers. After a byte is written,
the register address is automatically incremented by 1.
Remark: If the master writes to a nonexistent register, the slave must send
a 'not ACK' and also must not increment the index address.
slave generates an acknowledgment
master writes data to register K
slave generates an acknowledgment
master writes data to register K + 1
Rev. 01 — 24 May 2007
USB OTG transceiver with carkit support
© NXP B.V. 2007. All rights reserved.
ISP1302
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