ISPPAC-POWR604-01TN44E Lattice, ISPPAC-POWR604-01TN44E Datasheet - Page 10

• Manufacturer Part Number: ISPPAC-POWR604-01TN44E
• Description: Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
• Manufacturer: Lattice

Specifications of ISPPAC-POWR604-01TN44E

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: fpBGA-100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 1. V
Table 1 shows all possible comparator trip point voltage settings. The internal resistive divider allows ranges for
1.2V, 1.8V, 2.5V, 3.3V and 5.0V. There are 192 available voltages, ranging from 1.036V to 5.723V. In addition to the
192 voltage monitor trip points, the user can add additional resistors outside the device to divide down the voltage
and achieve virtually any voltage trip point. This allows the capability to monitor higher voltages such and 12V, 15V,
24V, etc. Voltage monitor trip points are set in the graphical user interface of the PAC-Designer software by simple
pull-down menus. The user simply selects the given range and corresponding trip point value. Attenuation and ref-
erence values are set internally using E
Figure 2 shows a single comparator, the attenuation network and reference used to program the monitor trip points.
Each of the six comparators are independently set in the same way.
Theory Of Operation
The ispPAC-POWR604 incorporates programmable voltage monitors along with digital inputs and outputs. The
eight macrocell PLD inputs are from the six voltage monitors and four digital inputs. There are two embedded pro-
grammable timers that interface with the PLD, along with an internal programmable oscillator.
The six independently programmable voltage monitors each have 192 programmable trip points.
Figure 2 shows a simplified schematic representation of one of these monitors.
1.All possible comparator trip voltages using internal attenuation settings.
1.2 low
1.036
1.046
1.056
1.066
1.076
1.087
1.096
1.107
1.117
1.127
1.137
1.147
1.157
1.168
1.178
1.188
MON
1.2 high
1.202
1.213
1.225
1.237
1.249
1.261
1.272
1.284
1.295
1.307
1.319
1.331
1.343
1.355
1.366
1.378
Trip Point Table
1.5 low
1.291
1.303
1.316
1.329
1.341
1.354
1.366
1.379
1.391
1.404
1.417
1.429
1.442
1.455
1.467
1.480
1.5 high
1.502
1.516
1.531
1.546
1.560
1.575
1.590
1.605
1.619
1.634
1.649
1.663
1.678
1.693
1.707
1.722
1
2
1.8 low
CMOS configuration bits internal to the device.
1.549
1.564
1.579
1.595
1.609
1.625
1.639
1.655
1.669
1.685
1.700
1.715
1.730
1.746
1.761
1.776
1.8 high
1.801
1.818
1.836
1.854
1.871
1.889
1.906
1.924
1.941
1.959
1.977
1.994
2.012
2.030
2.047
2.065
10
2.5 low
2.153
2.173
2.195
2.216
2.237
2.258
2.279
2.300
2.320
2.342
2.363
2.384
2.405
2.427
2.447
2.469
2.5 high
2.500
2.524
2.549
2.574
2.597
2.622
2.646
2.671
2.694
2.719
2.744
2.768
2.793
2.818
2.841
2.866
ispPAC-POWR604 Data Sheet
3.3 low
2.842
2.869
2.897
2.926
2.952
2.981
3.008
3.036
3.063
3.091
3.120
3.147
3.175
3.203
3.230
3.259
3.3 high
3.297
3.328
3.361
3.394
3.425
3.458
3.489
3.522
3.553
3.586
3.619
3.650
3.683
3.716
3.747
3.780
5.0 low
4.299
4.340
4.383
4.426
4.466
4.509
4.550
4.593
4.633
4.676
4.719
4.760
4.803
4.846
4.886
4.929
5.0 high
4.991
5.038
5.088
5.138
5.185
5.235
5.282
5.332
5.379
5.429
5.479
5.526
5.576
5.626
5.673
5.723