ISPPAC-POWR604-01TN44E Lattice, ISPPAC-POWR604-01TN44E Datasheet - Page 7

• Manufacturer Part Number: ISPPAC-POWR604-01TN44E
• Description: Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
• Manufacturer: Lattice

Specifications of ISPPAC-POWR604-01TN44E

• Number Of Voltages Monitored: 6
• Monitored Voltage: Adjustable
• Undervoltage Threshold: 1.03 V
• Overvoltage Threshold: 5.72 V
• Manual Reset: Not Resettable
• Watchdog: No Watchdog
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.25 V
• Supply Current (typ): 10000 uA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: fpBGA-100
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
DC Input Levels: IN1-IN4
Transient Characteristics
PLD Timing
Digital Glitch
Filter
t
t
t
t
1. External clock 1MHz. Open drain outputs with 2k pull-up resistor to V
Note: All the above parameters apply to signal paths from the digital inputs [IN1-IN4].
CMOS, LVCMOS3.3, LVTTL, TTL
LVCMOS2.5
Note: V
V
CO
SU
H
t
RST
PD
DDINP.
Symbol
DDINP
is the input supply pin for IN1-IN4 digital logic input pins. The logic threshold trip point of IN1-IN4 is dependent on the voltage at
Standard
Minimum pulse width to transition through
glitch filter.
Clock to Out Delay. Rising edge of clock to
output transition.
Time that input needs to be present when
using a registered function with the clock.
Time that input needs to be held valid after
the clock edge when using a registered
function with the clock.
Propagation delay internal to the
embedded PLD
RESET pulse width
Parameter
Over Recommended Operating Conditions
Min.
-0.3
-0.3
V
IL
(V)
Applied to IN1-IN4
Stable input before
clock edge (Note 1)
Data valid before clock
(Note 1)
Hold data after clock
7
DD
Conditions
.
Max.
0.8
0.7
ispPAC-POWR604 Data Sheet
Min.
20
25
20
0
Min.
2.0
1.7
Typ.
V
IH
(V)
Max.
300
90
Max.
5.5
5.5
Units
µs
ns
µs
µs
ns
µs