ISPPAC-POWR604-01TN44E Lattice, ISPPAC-POWR604-01TN44E Datasheet - Page 15

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ISPPAC-POWR604-01TN44E

Manufacturer Part Number
ISPPAC-POWR604-01TN44E
Description
Supervisory Circuits PROGRAMMABLE PWR SUPPLY CONTR
Manufacturer
Lattice
Datasheet

Specifications of ISPPAC-POWR604-01TN44E

Number Of Voltages Monitored
6
Monitored Voltage
Adjustable
Undervoltage Threshold
1.03 V
Overvoltage Threshold
5.72 V
Manual Reset
Not Resettable
Watchdog
No Watchdog
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.25 V
Supply Current (typ)
10000 uA
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Package / Case
fpBGA-100
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ISPPAC-POWR604-01TN44E
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Lattice Semiconductor
timers can cover a range from 32us to 524ms for the internal oscillator. Longer delays can be achieved by using the
external clock as an input.
Table 3. Timer Values
For design entry, the user can select the source for the clock and the PAC-Designer software will calculate the
appropriate delays in an easy-to-select menu format.
The control inputs for Timer1 and Timer2 can be driven by any of the eight PLD macrocell outputs. The reset for the
timers is a function of the Global Reset pin (RESET), a power-on reset or when the timer input goes low. The wave-
forms in Figure 6 show the basic timer start and reset functions. Timer and clock divider values are specified in dur-
ing the design phase using the PAC-Designer software, while simple pull-down menus allow the user to select the
clocking mode and the values for the timers and the PLD clock.
Figure 6. Timer Waveforms
Note that if the clock module is configured as “slave” (i.e. the CLK is an input), the actual time-out of the two timers
is determined by the external clock frequency.
1. Timer values based on 250kHz clock.
0.032 ms
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
2.048 ms
4.096 ms
62 kHz
÷ ÷ ÷ ÷ 4
Timer Gate
Timer Output
(From PLD)
(To PLD)
0.064 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
31.2 kHz
2.048ms
÷ ÷ ÷ ÷ 8
1
Timer
Start
16.384 ms
0.128 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
15.6 kHz
2.048ms
÷ ÷ ÷ ÷ 16
ProgrammableTimer
Timer Period
Delay
16.384 ms
32.768 ms
0.256 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
7.8 kHz
÷ ÷ ÷ ÷ 32
Expired
Timer
15
16.384 ms
32.768 ms
65.536 ms
0.512 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
3.9 kHz
Reset
Timer
÷ ÷ ÷ ÷ 64
Timer
Start
131.072 ms
16.384 ms
32.768 ms
65.536 ms
1.024 ms
4.096 ms
8.192 ms
2.048ms
ispPAC-POWR604 Data Sheet
2 kHz
÷ ÷ ÷ ÷ 128
ProgrammableTimer
Timer Period
Delay
131.072 ms
262.144 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
2.048ms
1 kHz
÷ ÷ ÷ ÷ 256
Expired
Timer
131.072 ms
262.144 ms
524.288 ms
16.384 ms
32.768 ms
65.536 ms
4.096 ms
8.192 ms
0.5 kHz
÷ ÷ ÷ ÷ 512

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