PSB3186FV14XP Infineon Technologies, PSB3186FV14XP Datasheet - Page 132

• Manufacturer Part Number: PSB3186FV14XP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MODED
XRES ... Transmitter Reset
The D-channel HDLC transmitter is reset and the XFIFOD is cleared of any data. This
command can be used by the microcontroller to abort a frame currently in transmission.
Note: After an XPR interrupt further data has to be written to the XFIFOD and the
4.1.7
Value after reset: C0
MDS2-0 ... Mode Select
Determines the message transfer mode of the HDLC controller, as follows:
MDS2-0 Mode
0
0
0
0
1
1
Data Sheet
0
0
1
1
0
1
appropriate Transmit Command (XTF) has to be written to the CMDRD register
again to continue transmission, when the current frame is not yet complete (see
also XPR in ISTAD).
During frame transmission, the 0-bit insertion according to the HDLC bit-stuffing
mechanism is done automatically.
0 Reserved
1 Reserved
0 Non-Auto
1 Non-Auto
0 Extended
0 Transparent
7
mode
mode
transparent
mode
mode 0
MDS2 MDS1 MDS0
MODED - Mode Register
H
Number of
Address
Bytes
1
2
–
0
1.Byte
TEI1,TEI2
SAP1,SAP2,
SAPG
–
132
RAC
Address Comparison
DIM2
Detailed Register Description
2.Byte
–
TEI1,TEI2,TEIG Two-byte
–
DIM1
0
DIM0
ISAC-SX TE
Remark
One-byte
address
compare.
address
compare.
No address
compare.
All frames
accepted.
RD/WR (22)
PSB 3186
2003-01-30