PSB3186FV14XP Infineon Technologies, PSB3186FV14XP Datasheet - Page 146

• Manufacturer Part Number: PSB3186FV14XP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

TR_STA
1: The phase deviation is 2 S-bits minus 9 oscillator periods plus analog delay plus
For general information please refer to
RLP ... Remote Line Loop
0: Remote Line Loop open
1: Remote Line Loop closed
For general information please refer to
4.2.4
Value after reset: 00
RINF ... Receiver INFO
00: Received INFO 0
01: Received any signal except INFO 0,2,4
10: Reserved INFO 2
11: Received INFO 4
SLIP ... SLIP Detected
A ’1’ in this bit position indicates that a SLIP is detected in the receive or transmit path.
ICV ... Illegal Code Violation
0: No illegal code violation is detected
1: llegal code violation (ANSI T1.605) in data stream is detected
FSYN ... Frame Synchronization State
0: The S/T receiver is not synchronized
1: The S/T receiver has synchronized to the framing bit F
LD ... Level Detection
0: No receive signal has been detected on the line.
1: Any receive signal has been detected on the line.
Data Sheet
delay of the external circuitry.
7
TR_STA - Transceiver Status Register
RINF
H
SLIP
ICV
Chapter
Chapter
146
0
3.3.7.
3.3.10.
FSYN
Detailed Register Description
0
0
LD
ISAC-SX TE
PSB 3186
2003-01-30
RD (33)