PSB3186FV14XP Infineon Technologies, PSB3186FV14XP Datasheet - Page 33

• Manufacturer Part Number: PSB3186FV14XP
• Manufacturer: Infineon Technologies

Specifications of PSB3186FV14XP

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

3.2.3
Special events in the device are indicated by means of a single interrupt output, which
requests the host to read status information from the device or transfer data from/to the
device.
Since only one interrupt request pin (INT) is provided, the cause of an interrupt must be
determined by the host reading the interrupt status registers of the device.
The structure of the interrupt status registers is shown in
Figure 8
All six interrupt bits in the ISTA register point at interrupt sources in the D-channel HDLC
Controller (ICD), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN), the
synchronous transfer (ST) and the auxiliary interrupts (AUXI).
All these interrupt sources are described in the corresponding chapters. After the device
has requested an interrupt activating the interrupt pin (INT), the host must read first the
device interrupt status register (ISTA) in the associated interrupt service routine. The
interrupt pin of the device remains active until all interrupt sources are cleared by reading
the corresponding interrupt register. Therefore it is possible that the interrupt pin is still
active when the interrupt service routine is finished.
Each interrupt indication of the interrupt status registers can selectively be masked by
setting the respective bit in the MASK register.
For some interrupt controllers or hosts it might be necessary to generate a new edge on
the interrupt line to recognize pending interrupts. This can be done by masking all
interrupts at the end of the interrupt service routine (writing FF
and write back the old mask to the MASK register.
Data Sheet
MASK
TRAN
MOS
Interrupt
AUX
CIC
ICD
ST
Interrupt Structure
Interrupt Status and Mask Registers
TRAN
ISTA
MOS
AUX
CIC
ICD
ST
MASKD
RME
RFO
XMR
RPF
XPR
XDU
D-channel
ISTAD
RME
RFO
XPR
XMR
XDU
RPF
STOV21
STOV20
STOV11
STOV10
MSTI
STI21
STI20
STI11
STI10
33
STOV21
STOV20
STOV11
STOV10
MOCR
STI21
STI20
STI11
STI10
MRE
MIE
STI
MASKTR
SQW
SQC
RIC
LD
Description of Functional Blocks
ACK21
ACK20
ACK11
ACK10
ASTI
ISTATR
MOSR
SQW
MDR
SQC
MER
MDA
MAB
RIC
LD
Figure
H
into the MASK register)
8.
CIX1
CI1E
AUXM
WOV
EAW
TIN2
TIN1
ISAC-SX TE
CIR0
CIC0
CIC1
3186_16.vsd
AUXI
WOV
EAW
TIN2
TIN1
PSB 3186
2003-01-30